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From: Nicholas Petreley <nicholas@petreley.com>
To: ignaciomonge@navegalia.com, linux-kernel@vger.kernel.org
Subject: Re: ATA 100
Date: Wed, 18 Apr 2001 23:24:17 -0700	[thread overview]
Message-ID: <3ADE8491.6080402@petreley.com> (raw)

Duh, mea stupida.  I misread your message.  You're trying to get 
the Promise IDE working at 100, no?  My Asus A7V133 has the 686b 
which does ATA100 without having to rely on the Promise chipset, 
and that seems to work fine. But if it helps to know, I've got an 
A7V with the 686a and I use the PDC20265 for my ATA100 drive. It 
boots with a message that says it's doing UDMA(100):

hde: 80041248 sectors (40981 MB) w/2048KiB Cache, 
CHS=79406/16/63, UDMA(100)

But /proc/ide/pdc202xx says:

                    PDC20265 Chipset.
--------------- drive0 ---------
DMA Mode:       UDMA 4

Shouldn't that be UDMA 5?

-Nick


I have the same motherboard, and it works fine for me.  Note the
80w cable detection.  Perhaps you've got a bad cable?

-Nick

----------VIA BusMastering IDE Configuration----------------
Driver Version:                     3.23
South Bridge:                       VIA vt82c686b
Revision:                           ISA 0x40 IDE 0x6
Highest DMA rate:                   UDMA100
BM-DMA base:                        0xd800
PCI clock:                          33MHz
Master Read  Cycle IRDY:            0ws
Master Write Cycle IRDY:            0ws
BM IDE Status Register Read Retry:  yes
Max DRDY Pulse Width:               No limit
-----------------------Primary IDE-------Secondary IDE------
Read DMA FIFO flush:          yes                 yes
End Sector FIFO flush:         no                  no
Prefetch Buffer:              yes                  no
Post Write Buffer:            yes                  no
Enabled:                      yes                 yes
Simplex only:                  no                  no
Cable Type:                   80w                 80w
-------------------drive0----drive1----drive2----drive3-----
Transfer Mode:       UDMA      UDMA      UDMA       PIO
Address Setup:       30ns      30ns      30ns     120ns
Cmd Active:          90ns      90ns      90ns      90ns
Cmd Recovery:        30ns      30ns      30ns      30ns
Data Active:         90ns      90ns      90ns     330ns
Data Recovery:       30ns      30ns      30ns     270ns
Cycle Time:          20ns      20ns      60ns     600ns
Transfer Rate:  100.0MB/s 100.0MB/s  33.3MB/s   3.3MB/s



             reply	other threads:[~2001-04-19  6:24 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2001-04-19  6:24 Nicholas Petreley [this message]
  -- strict thread matches above, loose matches on Subject: below --
2001-04-19 14:50 ATA 100 David Balazic
2001-04-19 14:46 David Balazic
2001-04-19 16:15 ` Vojtech Pavlik
2001-04-19  6:01 Nicholas Petreley

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