Re: VIA KT133A / athlon / MMX

Kurt Garloff
2001-07-30T13:47:41Z

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Hi Daniela,

On Mon, Jul 30, 2001 at 08:04:54AM +0200, Daniela Engert wrote:
> On Sun, 29 Jul 2001 22:28:30 +0200, Kurt Garloff wrote:
>
> >Me neither. I was hoping that only a bit differs. Unfortunately that's not
> >the case, so I need to have a look in the datasheet.
> >But those are not publically available :-(
> >Anybody having them?
>
> Try to get a clue yourself from the WPCREDIT KT133 plugin (see below,
> stripped down to the differing registers). Some differences look
> suspicious to me...

Hey thanks!

> [54:6]=Probe Next Tag State T1 0=disable 1=enable

Main suspect. (Should be 0)

> [54:0]=Fast Write-to-Read 0=disable 1=enable

Third candidate. (Should be 0)

> [68:4]=DRAM Data Latch Delay 0=Latch 1=Delay latch

Second candidate (Should be 1)

> [68:2]=Burst Refresh(4 times) 0=disable 1=enable

Fourth candidate (Should be 0?)

> [6B:5]=Fast Read to Write t-a 0=disable 1=enable

Should this one match 54:0 (third candidate)?

> [6B:1]=Virtual Channel-DRAM 0=disable 1=enable

Strange, why does this one differ between the configs.

OK, I'll come up with a kernel patches (driver/pci/quirks ...)
for people to test.

Regards,
--
Kurt Garloff <garloff@suse.de> Eindhoven, NL
GPG key: See mail header, key servers Linux kernel development
SuSE GmbH, Nuernberg, DE SCSI, Security

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