From: Holger Lubitz <h.lubitz@internet-factory.de>
To: linux-kernel@vger.kernel.org
Subject: Re: [FAQ?] More ram=less performance (maximum cacheable RAM)
Date: Tue, 28 Aug 2001 16:23:52 +0200 [thread overview]
Message-ID: <3B8BA978.47EF9D77@internet-factory.de> (raw)
In-Reply-To: <3B82B988.50DE308A@iname.com> <200108211957.f7LJvEt20846@vindaloo.ras.ucalgary.ca>
Richard Gooch proclaimed:
> Er, are you sure about this? The problem isn't the size of your cache,
> it's the size of your TAG RAM. That's a different beast.
Cachable memory area is a function of cache size, tag size and cache
mode (wb or wt - first needs dirty tag, second doesn't). With VIA MVP3
boards for example, cachable memory depends on the size of the cache.
Which is why most of the boards with this chipset had 1 MB level 2 cache
(enough for 128 mb with writeback or 256 mb with writethrough), some
even had 2 MB (for twice that).
Holger
next prev parent reply other threads:[~2001-08-28 14:23 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-08-21 19:42 [FAQ?] More ram=less performance (maximum cacheable RAM) Luca Montecchiani
2001-08-21 19:57 ` Richard Gooch
2001-08-21 20:38 ` Luca Montecchiani
2001-08-21 21:53 ` Robert Love
2001-08-22 6:27 ` Luca Montecchiani
2001-08-22 11:12 ` Wakko Warner
2001-08-22 21:26 ` idalton
2001-08-23 5:19 ` Richard Gooch
2001-08-23 11:35 ` Luca Montecchiani
2001-08-28 14:23 ` Holger Lubitz [this message]
-- strict thread matches above, loose matches on Subject: below --
2001-08-21 22:01 Samium Gromoff
2001-08-22 9:49 Samium Gromoff
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