Re: Context switch times

Richard Gooch
2001-10-04T21:39:34Z

David S. Miller writes:
> From: arjan@fenrus.demon.nl
> Date: Thu, 04 Oct 2001 22:14:13 +0100
>
> > Comments?
>
> 2.4.x supports SSE on pentium III/athlons, so the SSE registers need to be
> saved/restored on a taskswitch as well.... that's not exactly free.
>
> lat_ctx doesn't execute any FPU ops. So at worst this happens once
> on GLIBC program startup, but then never again.

Has something changed? Last I looked, the whole lmbench timing harness
was based on using the FPU. That was the cause of the big argument
Larry and I had some years back: my context switch benchmark didn't
use the FPU, and thus was more sensitive to variations (such as cache
misses due to aliasing).

Regards,

Richard....
Permanent: rgooch@atnf.csiro.au
Current: rgooch@ras.ucalgary.ca