[PATCH] Pentium IV cacheline size.

[PATCH] Pentium IV cacheline size.

[Dave Jones]

Currently, we're using a L1_CACHE_SHIFT value of 7
for Pentium 4, which equates to 128 byte cache lines.
Curious, I dumped the info on the only P4 I could find,
and noticed they were 64 byte.
Upon checking the documentation, they're 64 byte there too. 
Is this just a thinko on someones part, or was there a
rationale behind this that I've not realised ?

If it is wrong, patch below sets it back to 64 bytes.

regards,

Dave.


diff -urN --exclude-from=/home/davej/.exclude linux/arch/i386/config.in linux-dj/arch/i386/config.in
--- linux/arch/i386/config.in	Fri Oct 12 16:29:57 2001
+++ linux-dj/arch/i386/config.in	Sat Oct 13 12:40:19 2001
@@ -108,7 +108,7 @@
    define_bool CONFIG_X86_USE_PPRO_CHECKSUM y
 fi
 if [ "$CONFIG_MPENTIUM4" = "y" ]; then
-   define_int  CONFIG_X86_L1_CACHE_SHIFT 7
+   define_int  CONFIG_X86_L1_CACHE_SHIFT 6
    define_bool CONFIG_X86_TSC y
    define_bool CONFIG_X86_GOOD_APIC y
    define_bool CONFIG_X86_PGE y

-- 
| Dave Jones.                    http://www.codemonkey.org.uk
| SuSE Labs .

Re: [PATCH] Pentium IV cacheline size.

[Mikael Pettersson]

On Sat, 13 Oct 2001 12:57:33 +0100, Dave Jones wrote:
>Currently, we're using a L1_CACHE_SHIFT value of 7
>for Pentium 4, which equates to 128 byte cache lines.
>Curious, I dumped the info on the only P4 I could find,
>and noticed they were 64 byte.
>Upon checking the documentation, they're 64 byte there too. 
>Is this just a thinko on someones part, or was there a
>rationale behind this that I've not realised ?

According to the P4 and Xeon optimisation manual (#248966-03), the
L1 cache has a 64-byte line size and the L2 cache has a 128-byte
line size. (Page 1-18, Table 1-1.) Perhaps someone just confused
the two, or the distinction wasn't known when the initial P4
support was added to the kernel.

/Mikael

Re: [PATCH] Pentium IV cacheline size.

[Dave Jones]

On Sat, 13 Oct 2001, Mikael Pettersson wrote:

> According to the P4 and Xeon optimisation manual (#248966-03), the
> L1 cache has a 64-byte line size and the L2 cache has a 128-byte
> line size. (Page 1-18, Table 1-1.) Perhaps someone just confused

Great, conflicting documentation.
#24547203 (Vol3 : System programming guide) has this to say..
(page 325)
"The cache lines for the L1 and L2 caches in the Pentium 4 processor
 are 64 bytes wide"


regards,

Dave.

-- 
| Dave Jones.        http://www.codemonkey.org.uk
| SuSE Labs

Re: [PATCH] Pentium IV cacheline size.

[Mark Hahn]

> Currently, we're using a L1_CACHE_SHIFT value of 7
> for Pentium 4, which equates to 128 byte cache lines.
> Curious, I dumped the info on the only P4 I could find,
> and noticed they were 64 byte.

the value is correct, but the name should be SMP rather than L1,
since we (only?) use the value for aligning data to avoid false sharing.

regards, mark hahn

Re: [PATCH] Pentium IV cacheline size.

[Linus Torvalds]

On Sat, 13 Oct 2001, Dave Jones wrote:
>
> Currently, we're using a L1_CACHE_SHIFT value of 7
> for Pentium 4, which equates to 128 byte cache lines.

Well, the fact is, that from a SMP standpoint, the 128 bytes is the
correct one: the L2 is 128 bytes wide.

		Linus

Re: [PATCH] Pentium IV cacheline size.

[Manfred Spraul]

 
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Linus wrote:
> On Sat, 13 Oct 2001, Dave Jones wrote:
> >
> > Currently, we're using a L1_CACHE_SHIFT value of 7
> > for Pentium 4, which equates to 128 byte cache lines.
> 
> Well, the fact is, that from a SMP standpoint, the 128 bytes is the
> correct one: the L2 is 128 bytes wide.

The 128 bytes are split into 2 sectors - I'm not sure if 128 or 64 bytes
is appropriate.

<<<<<
The L2 cache is a 256K-byte cache that holds both instructions
that miss the Trace Cache and data that miss the L1 data cache.
The L2 cache is organized as an 8-way set-associative cache with
128 bytes per cache line. These 128-byte cache lines consist of
two 64-byte sectors. A miss in the L2 cache typically initiates
two 64-byte access requests to the system bus to fill both halves
of the cache line.
<<<<<
http://developer.intel.com/technology/itj/q12001/articles/art_2.htm

--
	Manfred