From: Manfred Spraul <manfred@colorfullife.com>
To: Davide Libenzi <davidel@xmailserver.org>
Cc: Shuji YAMAMURA <yamamura@flab.fujitsu.co.jp>,
lkml <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] task_struct + kernel stack colouring ...
Date: Wed, 05 Dec 2001 21:33:56 +0100 [thread overview]
Message-ID: <3C0E84B4.1070808@colorfullife.com> (raw)
In-Reply-To: <Pine.LNX.4.40.0112051103100.1644-100000@blue1.dev.mcafeelabs.com>
Davide Libenzi wrote
>
>
>By adding three bits of colouring you're going to cut the collision of
>about 1/8.
>
No, Shuji is right:
You have just shifted the problem, without reducing collisions.
256 kB, 4 way cache with 32 byte linesize.
cacheline == bits 15..5
offset within cacheline: bits 4..0
The colouring must depend on more than just bits 13 to 15 - if these
bits are different, then the access goes into a different line even
without colouring, there won't be a collision.
Shuij, I don't understand why you need both a shift and a modulo:
address % odd_number should generate a random distribution (i.e. all
bits affect the result), even without the shift.
--
Manfred
next prev parent reply other threads:[~2001-12-05 20:34 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-12-04 2:13 [PATCH] task_struct + kernel stack colouring Davide Libenzi
2001-12-05 12:22 ` Shuji YAMAMURA
2001-12-05 19:23 ` Davide Libenzi
2001-12-05 20:33 ` Manfred Spraul [this message]
2001-12-05 21:00 ` Davide Libenzi
2001-12-06 0:12 ` kumon
2001-12-06 8:34 ` Shuji YAMAMURA
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