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Date: Tue, 07 May 2002 16:23:28 -0500
From: Dave Engebretsen <engebret@vnet.ibm.com>
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To: Alan Cox <alan@lxorguk.ukuu.org.uk>
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Subject: Re: Memory Barrier Definitions
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Alan Cox wrote:
> 
> > forms of processor memory barrier instructions.  It is _very_ expensive
> I think I follow
> 
> You have
> 
>         Compiler ordering
>         CPU v CPU memory ordering
>         CPU v I/O memory ordering
>         I/O v I/O memory ordering
> 

Yep, that is a good summary.  And the problem arises from the very large
penalty for the syncronization form used for CPU v I/O ordering.  You
only want to pay that when necessary, certainly not when only CPU v CPU
ordering is required.  The difference can be on the order of a 1000
cycles (depending on many factors, of course).

Dave.