Re: Memory Barrier Definitions

[Dave Engebretsen <engebret@vnet.ibm.com>]

Dave Engebretsen wrote:
> 
> justincarlson@cmu.edu wrote:
> >
> > On Tue, 2002-05-07 at 16:27, Alan Cox wrote:
> > > and our current heirarchy is a little bit more squashed than that. I'd
> > > agree. We actually hit a corner case of this on the IDT winchip x86 where
> > > we run relaxed store ordering and have to define wmb() as a locked add of
> > > zero to the top of stack - which does have a penalty that isnt needed
> > > for CPU ordering.
> > >
> > > How much of this impacts Mips64 ?
> >
> > In terms of the MIPS{32|64} ISA, the current primitives seem fine;
> > there's only 1 option defined in the ISA:  'sync'.  Order for all
> > off-cache accesses is guaranteed around a sync.
> >
> > It gets a bit more complicated when you talk about what particular
> > implementations do, and ordering rules for uncached vs cached accesses,
> > but to the best of my knowledge there aren't any fundamental problems as
> > described for the PPC.
> >
> > -Justin

I am curious what the definition of memory barriers is for IA64, Sparc,
and x86-64.  

>From what I can tell, sparc and x86-64 are like alpha and map directly
to the existing mb, wmb, and rmb semantics, incluing ordering between
system memory and I/O space.  Is that an accurate assesment?

IA64 has both the mf and mf.a instructions, one for system memory the
other for I/O space.  What is required for ordering of references
between the spaces?  That is not clear to me looking at the ia64
headers.

Thanks for any input -

Dave.