Re: Memory Barrier Definitions

[Manfred Spraul <manfred@colorfullife.com>]

 	
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>
> An example of where these primitives get us into trouble is the use of
> wmb() to order two stores which are only to system memory (where a
> lwsync would do for ppc64) and for a store to system memory followed by
> a store to I/O (many examples in drivers).
>
2 questions:

1) Does that only affect memory barriers, or both memory barriers and
spinlocks?

example (from drivers/net/natsemi.c)

cpu0:
	spin_lock(&lock);
	writew(1, ioaddr+PGSEL);
	...
	writew(0, ioaddr+PGSEL);
	spin_unlock(&lock);

cpu1:
	spin_lock(&lock);
	readw(ioaddr+whatever);	// assumes that the register window is 0.

writew(1, ioaddr+PGSEL) selects a register window of the NIC. Are writew
and the spinlock synchonized on ppc64?

2) when you write "system memory", is that memory allocated with
kmalloc/gfp, or also memory allocated with pci_alloc_consistent()?

I've always assumed that
	pci_alloc_consistent_ptr->data=0;
	writew(0, ioaddr+TRIGGER);

is ordered, i.e. the memory write happens before the writew. Is that
guaranteed?

--
	Manfred