Re: PCI DMA to small buffers on cache-incoherent arch

Oliver Neukum
2002-06-11T12:06:29Z

Am Dienstag, 11. Juni 2002 10:15 schrieb David S. Miller:
> From: Oliver Neukum <oliver@neukum.name>
> Date: Tue, 11 Jun 2002 10:07:19 +0200
>
> Are there really PCI controllers which have to physically write
> much more than is transfered ?
>
> On sparc64 the cacheline size can be either 64 or 128 bytes.
> It's a bus characteristic, so we have to get at the PCI
> controller info.

A sparc64 is unlikely to be short on memory, or is it ?
What's wrong with always aligning on 128 bytes on sparc64 ?
A runtime check would be expensive.

Regards
Oliver