Re: PCI DMA to small buffers on cache-incoherent arch

David S. Miller
2002-06-11T08:19:36Z

From: Oliver Neukum <oliver@neukum.name>
Date: Tue, 11 Jun 2002 10:07:19 +0200

Are there really PCI controllers which have to physically write
much more than is transfered ?

On sparc64 the cacheline size can be either 64 or 128 bytes.
It's a bus characteristic, so we have to get at the PCI
controller info.