* [PATCH]: { 2.5 } Correcting comment in include/asm-i386/tlbflush.h
@ 2002-07-01 11:32 Manik Raina
0 siblings, 0 replies; only message in thread
From: Manik Raina @ 2002-07-01 11:32 UTC (permalink / raw)
To: mingo, davej; +Cc: torvalds, linux-kernel
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TLB flush happens when the CR3 register is written to. Comment is
misleading ....
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diff -u -U 6 -r linux-2.5.24/include/asm-i386/tlbflush.h nice/include/asm-i386/tlbflush.h
--- linux-2.5.24/include/asm-i386/tlbflush.h Fri Jun 21 04:23:51 2002
+++ nice/include/asm-i386/tlbflush.h Mon Jul 1 16:54:31 2002
@@ -7,14 +7,14 @@
#define __flush_tlb() \
do { \
unsigned int tmpreg; \
\
__asm__ __volatile__( \
- "movl %%cr3, %0; # flush TLB \n" \
- "movl %0, %%cr3; \n" \
+ "movl %%cr3, %0; \n" \
+ "movl %0, %%cr3; # flush TLB \n" \
: "=r" (tmpreg) \
:: "memory"); \
} while (0)
/*
* Global pages have to be flushed a bit differently. Not a real
@@ -23,14 +23,14 @@
#define __flush_tlb_global() \
do { \
unsigned int tmpreg; \
\
__asm__ __volatile__( \
"movl %1, %%cr4; # turn off PGE \n" \
- "movl %%cr3, %0; # flush TLB \n" \
- "movl %0, %%cr3; \n" \
+ "movl %%cr3, %0; \n" \
+ "movl %0, %%cr3; # flush TLB \n" \
"movl %2, %%cr4; # turn PGE back on \n" \
: "=&r" (tmpreg) \
: "r" (mmu_cr4_features & ~X86_CR4_PGE), \
"r" (mmu_cr4_features) \
: "memory"); \
} while (0)
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2002-07-01 11:32 [PATCH]: { 2.5 } Correcting comment in include/asm-i386/tlbflush.h Manik Raina
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