Re: [PATCH] flush_cache_page while pte valid

David S. Miller
2002-11-12T21:40:54Z

From: Rik van Riel <riel@conectiva.com.br>
Date: Tue, 12 Nov 2002 12:49:50 -0200 (BRST)

On Mon, 11 Nov 2002, David S. Miller wrote:
> The flush merely writes back the data, a copy-back operation, fully L2
> cache coherent. All cpus will see correct data if an intermittant
> store occurs.

The CPUs will, but the harddisk might not.

We really need to get this right in the swapout path.

We do get it right, watch:

1) remove last mapping instance of page

-> MM level cache flush pushes it permanently to ram
in full view of DMA activity

2) remove last mapping, but new one appears as we swap out

-> no problem we'll see one of several instances of the
page and we'll need to reswap it out later anyways
if someone currently writes to it

I know this because I tested this extensively ages ago on sparc32
where it really mattered.