[CFT,PATCH] Do not taint AMD non-MP cpus if only one cpu is present

[Manfred Spraul <manfred@colorfullife.com>]

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smp_store_cpu_info() sets TAINT_UNSAFE_SMP as soon as it finds an K7 cpu 
that doesn't support SMP, even if only one cpu is present. This is wrong 
- it's ok to run an SMP kernel with a non-MP cpu, as long as only one 
cpu is present.
Unfortunately neither num_online_cpus() nor num_booting_cpu() work when 
smp_store_cpu_info() is called.

The attached patch moves that check into an __initcall.
It's tested on my uniprocessor Duron, but not on real SMP.

Could someone with an Athlon-non-MP SMP setup check that the kernel 
still complains about the non-certified setup?

Thanks,
    Manfred

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--- 2.5/arch/i386/kernel/smpboot.c	2003-01-04 10:18:05.000000000 +0100
+++ build-2.5/arch/i386/kernel/smpboot.c	2003-01-04 10:53:15.000000000 +0100
@@ -132,41 +132,57 @@
 		 * Remember we have B step Pentia with bugs
 		 */
 		smp_b_stepping = 1;
+}
 
-	/*
-	 * Certain Athlons might work (for various values of 'work') in SMP
-	 * but they are not certified as MP capable.
-	 */
-	if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
+static int __init check_smp_support(void)
+{
+	int i;
+
+	if (num_online_cpus() == 1)
+		return 0;
 
-		/* Athlon 660/661 is valid. */	
-		if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1)))
-			goto valid_k7;
-
-		/* Duron 670 is valid */
-		if ((c->x86_model==7) && (c->x86_mask==0))
-			goto valid_k7;
+	for(i=0;i<NR_CPUS;i++) {
+		struct cpuinfo_x86 *c = cpu_data + i;
 
+		if (!cpu_online(i))
+			continue;
 		/*
-		 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
-		 * It's worth noting that the A5 stepping (662) of some Athlon XP's
-		 * have the MP bit set.
-		 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
+		 * Certain Athlons might work (for various values of 'work') in SMP
+		 * but they are not certified as MP capable.
 		 */
-		if (((c->x86_model==6) && (c->x86_mask>=2)) ||
-		    ((c->x86_model==7) && (c->x86_mask>=1)) ||
-		     (c->x86_model> 7))
-			if (cpu_has_mp)
+		if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
+
+			/* Athlon 660/661 is valid. */	
+			if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1)))
 				goto valid_k7;
 
-		/* If we get here, it's not a certified SMP capable AMD system. */
-		printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n");
-		tainted |= TAINT_UNSAFE_SMP;
-	}
+			/* Duron 670 is valid */
+			if ((c->x86_model==7) && (c->x86_mask==0))
+				goto valid_k7;
+
+			/*
+			 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
+			 * It's worth noting that the A5 stepping (662) of some Athlon XP's
+			 * have the MP bit set.
+			 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
+			 */
+			if (((c->x86_model==6) && (c->x86_mask>=2)) ||
+			    ((c->x86_model==7) && (c->x86_mask>=1)) ||
+			     (c->x86_model> 7))
+				if (cpu_has_mp)
+					goto valid_k7;
+
+			/* If we get here, it's not a certified SMP capable AMD system. */
+			printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n");
+			tainted |= TAINT_UNSAFE_SMP;
+		}
 
-valid_k7:
-	;
+	valid_k7:
+		;
+	}
+	return 0;
 }
+__initcall(check_smp_support);
 
 /*
  * TSC synchronization.