From: "David B. Stevens" <dsteven3@maine.rr.com>
To: Jamie Lokier <jamie@shareable.org>
Cc: michaelc <michaelc@turbolinux.com.cn>, linux-kernel@vger.kernel.org
Subject: Re: about PENTIUM4 cache line
Date: Sun, 17 Aug 2003 16:36:51 -0400 [thread overview]
Message-ID: <3F3FE763.20503@maine.rr.com> (raw)
In-Reply-To: <20030817202534.GC3543@mail.jlokier.co.uk>
What's even more interesting is the following:
tux:/usr/src/linux-2.6.0-test3 # grep -r "CONFIG_X86_L1_CACHE_SHIFT" *
arch/i386/defconfig:CONFIG_X86_L1_CACHE_SHIFT=7
arch/x86_64/defconfig:CONFIG_X86_L1_CACHE_SHIFT=6
include/asm-x86_64/cache.h:#define L1_CACHE_SHIFT
(CONFIG_X86_L1_CACHE_SHIFT)
include/linux/autoconf.h:#define CONFIG_X86_L1_CACHE_SHIFT 5
include/asm-i386/cache.h:#define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT)
include/asm/cache.h:#define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT)
include/config/x86/l1/cache/shift.h:#define CONFIG_X86_L1_CACHE_SHIFT 5
tux:/usr/src/linux-2.6.0-test3 #
Life sure is interesting.
Cheers,
Dave
Jamie Lokier wrote:
> michaelc wrote:
>
>> I read the Intel IA-32 developer's manual recently, and I found
>> the cache lines for L1 and L2 caches in Pentium4 are 64 bytes
>> wide, but the thing make me confused is that the default value
>> CONFIG_X86_L1_CACHE_SHIFT option in 2.4.x kernel is 7, why it's
>> not 6? Any expanation about this would be appreciated!
>
>
> I don't recall seeing an answer to this.
> Was there one?
>
> Cheers,
> -- Jamie
> -
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next prev parent reply other threads:[~2003-08-17 20:34 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-03-09 9:03 about PENTIUM4 cache line michaelc
2001-08-08 11:52 ` shutdown on pressing the ATX power button Sergei Haller
2001-08-09 17:56 ` Pavel Machek
2003-08-17 20:25 ` about PENTIUM4 cache line Jamie Lokier
2003-08-17 20:36 ` David B. Stevens [this message]
2003-08-17 20:45 ` Dave Jones
2003-08-17 20:58 ` David B. Stevens
2003-08-17 20:42 ` Dave Jones
2003-08-17 22:52 ` Philippe Elie
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