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From: Manfred Spraul <manfred@colorfullife.com>
To: Adrian Bunk <bunk@fs.tum.de>
Cc: linux-kernel@vger.kernel.org, peter_daum@t-online.de
Subject: Re: [2.4 patch] fix CONFIG_X86_L1_CACHE_SHIFT
Date: Sun, 07 Sep 2003 22:36:19 +0200	[thread overview]
Message-ID: <3F5B96C3.1060706@colorfullife.com> (raw)

Adrian wrote:

>With CONFIG_M686 CONFIG_X86_L1_CACHE_SHIFT was set to 5, but a Pentium 4 
>requires 7.
>  
>
Why requires? On x86, the cpu caches are fully coherent. A too small L1 
cache shift results in false sharing on SMP, but it shouldn't cause the 
described problems.

And obviously: Pentium II cpus have a 32 byte cache line, increasing the 
L1 setting to 128 bytes only helps by chance.

My bet is that someone overwrites critical memory structures, and with 
more padding, the critical stuff is further away.

--
    Manfred



             reply	other threads:[~2003-09-07 20:36 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2003-09-07 20:36 Manfred Spraul [this message]
2003-09-08 14:20 ` [2.4 patch] fix CONFIG_X86_L1_CACHE_SHIFT Adrian Bunk
2003-09-08 17:07   ` Jamie Lokier
2003-09-08 17:24     ` Jeff Garzik
2003-09-08 19:45       ` Manfred Spraul
2003-09-09 14:49         ` Peter Daum
     [not found] <20030907195557.GK14436@fs.tum.de.suse.lists.linux.kernel>
2003-09-07 20:30 ` Andi Kleen
2003-09-07 21:39   ` Dave Jones
2003-09-08  8:15     ` Peter Daum
     [not found] ` <Pine.LNX.4.30.0309072228110.9987-100000@swamp.bayern.net.suse.lists.linux.kernel>
2003-09-07 21:57   ` Andi Kleen
  -- strict thread matches above, loose matches on Subject: below --
2003-09-07 19:55 Adrian Bunk
2003-09-07 20:59 ` Peter Daum

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