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Date: Tue, 16 Dec 2003 12:55:51 -0500
From: Jeff Garzik <jgarzik@pobox.com>
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To: arjanv@redhat.com
CC: Vladimir Kondratiev <vladimir.kondratiev@intel.com>,
       Linus Torvalds <torvalds@osdl.org>, greg@kroah.com,
       linux-kernel@vger.kernel.org, Alan Cox <alan@redhat.com>,
       Marcelo Tosatti <marcelo@conectiva.com.br>, Martin Mares <mj@ucw.cz>
Subject: Re: PCI Express support for 2.4 kernel
References: <3FDCC171.9070902@intel.com> <3FDCCC12.20808@pobox.com>	 <3FDD8691.80206@intel.com> <20031215103142.GA8735@iram.es>	 <3FDDACA9.1050600@intel.com> <1071494155.5223.3.camel@laptop.fenrus.com>	 <3FDDBDFE.5020707@intel.com>	 <Pine.LNX.4.58.0312151154480.1631@home.osdl.org>	 <3FDEDC77.9010203@intel.com>  <3FDF3C6C.9030609@pobox.com> <1071596889.5223.7.camel@laptop.fenrus.com>
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Arjan van de Ven wrote:
> On Tue, 2003-12-16 at 18:10, Jeff Garzik wrote:
>>This is going to choke some hardware, I guarantee.
>>You always want to make sure your flush is of the same size at the 
>>write.  Reading a byte from an address that the hardware defines as 
>>"32-bit writes only" can get ugly real quick ;-)
> 
> 
> also reading back addr might not be the best choice in case some
> registers have side effects on reading, it's probably better to read
> back an address that is known to be ok to read (like the vendor ID
> field)


Hum.  Never seen this in a PCI config register, but it's certainly 
possible...  good point.

	Jeff