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From: Jeff Garzik <jgarzik@pobox.com>
To: Mickael Marchand <marchand@kde.org>
Cc: linux-kernel@vger.kernel.org,
	Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl>
Subject: Re: [PATCH] adaptec 1210sa
Date: Tue, 30 Dec 2003 18:51:38 -0500	[thread overview]
Message-ID: <3FF20F8A.20408@pobox.com> (raw)
In-Reply-To: <200312220305.29955.marchand@kde.org>

Mickael Marchand wrote:
> --- /usr/src/linux-2.6.0/drivers/scsi/sata_sil.c	2003-12-21 13:30:58.000000000 +0100
> +++ linux-2.6.0/drivers/scsi/sata_sil.c	2003-12-22 02:46:32.000000000 +0100
> @@ -276,6 +276,16 @@
>  		goto err_out_regions;
>  	}
>  
> +	//let's have fun
> +	u8 v; 
> +	pci_read_config_byte(pdev, 0x8a, &v);
> +	int mask = 0x3f; //clear 6 and 7 bits
> +	if (v & ~mask) {
> +		printk("Reenabling interrupts because Adaptec's BIOS disables them\n" );
> +		v &= mask;
> +		pci_write_config_byte(pdev, 0x8a, v);
> +	}
> +
>  	memset(probe_ent, 0, sizeof(*probe_ent));
>  	INIT_LIST_HEAD(&probe_ent->node);
>  	probe_ent->pdev = pdev;


Actually, ignore that last question.  The SII docs indicate these bits 
are present in the standard SII 3112 chip, so the driver should just 
make sure to do this unconditionally.

Bart, the above applies to siimage.c as well.  The following are equal:
* PCI config reg 0x8a (byte), bits 6/7
* PCI config reg 0x88 (dword), bits 22/23
* MMIO offset 0x48 (dword), bits 22/23

The lower bit masks IDE0 interrupts, and the higher bit masks IDE1 
interrupts.

	Jeff




  parent reply	other threads:[~2003-12-30 23:52 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2003-12-22  2:05 [PATCH] adaptec 1210sa Mickael Marchand
2003-12-30 23:34 ` Jeff Garzik
2003-12-30 23:57   ` Justin T. Gibbs
2003-12-30 23:55     ` Jeff Garzik
2003-12-31  0:10   ` Hugo Mills
2003-12-30 23:51 ` Jeff Garzik [this message]
2003-12-31  0:20 ` Jeff Garzik
2003-12-31 11:25   ` Mickael Marchand
2004-01-03 20:46   ` Mickael Marchand

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