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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af6358acb2asm717167866b.56.2025.07.30.02.39.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 30 Jul 2025 02:39:21 -0700 (PDT) Message-ID: <3c69deb7-3a23-4627-a64f-3179785bf6f5@oss.qualcomm.com> Date: Wed, 30 Jul 2025 11:39:18 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/4] clk: qcom: apss-ipq5424: Add ipq5424 apss clock controller To: Varadarajan Narayanan , andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, konradybcio@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, ilia.lin@kernel.org, djakov@kernel.org, quic_srichara@quicinc.com, quic_mdalam@quicinc.com, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org References: <20250730081316.547796-1-quic_varada@quicinc.com> <20250730081316.547796-3-quic_varada@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250730081316.547796-3-quic_varada@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzMwMDA2NyBTYWx0ZWRfX/4liSAE1cmLj ZEagD2463sNp4jRFX1dffwmnZ9Iqh/USh06Ea/BXJx4nlUUxlIqezc4pZfKQY2rY1FXN5i+4SLi ts1jPpBJZwT8k4bRnj1XfMq/nsaytncUgHnFKlSmnKuf53q3JQUSWCK7SjYgwrku/g7Vr2C/gNK DlZiCU+MBUTXwmRYNMJ1QQhsXtcozMWBZbOGLnNVEEyAXLg/gbsjXRXf4zEDmEKICx7kH5vlgM6 F0dxOBtAjf1KR+7lz0MsdK9wAoIIB5YiCnsC3gTCb2Wh8B9P/s+27fmgXyF/Cv8IjNilizcNnow XNNHgRhENCqKqwExYe/jhB4J/ifhSGTdo+lKSYijVgJhBsIO1uYEWwDFCwtiREeeQNDJv/MATgy qzn1vcex5J3NXMAwQnFiSciVc7sirfJmi2NSdCueO6lANaaTnVEFdYyvdNXVNOdFxFq3dhqr X-Proofpoint-ORIG-GUID: JOZ-fCA2xDhJiitoXhEesOOjWbng3krD X-Authority-Analysis: v=2.4 cv=ea89f6EH c=1 sm=1 tr=0 ts=6889e84c cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=i-JfjlNmehoY5ENsB_0A:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: JOZ-fCA2xDhJiitoXhEesOOjWbng3krD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-30_03,2025-07-30_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 suspectscore=0 bulkscore=0 adultscore=0 clxscore=1015 spamscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507300067 On 7/30/25 10:13 AM, Varadarajan Narayanan wrote: > From: Sricharan Ramabadhran > > CPU on Qualcomm ipq5424 is clocked by huayra PLL with RCG support. > Add support for the APSS PLL, RCG and clock enable for ipq5424. > The PLL, RCG register space are clubbed. Hence adding new APSS driver > for both PLL and RCG/CBC control. Also the L3 cache has a separate pll > and needs to be scaled along with the CPU and is modeled as an ICC clock. > > Co-developed-by: Md Sadre Alam > Signed-off-by: Md Sadre Alam > Signed-off-by: Sricharan Ramabadhran > [ Removed clock notifier, moved L3 pll to icc-clk, used existing > alpha pll structure ] > Signed-off-by: Varadarajan Narayanan > --- [...] > +static struct clk_alpha_pll ipq5424_apss_pll = { > + .offset = 0x0, > + .config = &apss_pll_config, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_2290], > + .flags = SUPPORTS_DYNAMIC_UPDATE, > + .clkr = { > + .enable_reg = 0x0, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "apss_pll", > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "xo-board-clk", This is not consistent with your dt-bindings. You should instead define an enum that reflects them and use .index (see e.g. gcc-sm8750.c) > + }, > + .parent_names = (const char *[]){ "xo-board-clk"}, > + .num_parents = 1, > + .ops = &clk_alpha_pll_huayra_ops, > + }, > + }, > +}; > + > +static const struct clk_parent_data parents_apss_silver_clk_src[] = { > + { .fw_name = "xo-board-clk" }, > + { .fw_name = "clk_ref" }, Similarly here, neither one exists Konrad