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[91.79.175.49]) by smtp.googlemail.com with ESMTPSA id e16sm13015440pfn.46.2019.02.02.05.30.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 02 Feb 2019 05:30:47 -0800 (PST) Subject: Re: [PATCH V5 2/7] clocksource: tegra: add Tegra210 timer support To: Joseph Lo , Jon Hunter , Thierry Reding , Daniel Lezcano , Thomas Gleixner Cc: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Thierry Reding References: <20190201033621.16814-1-josephl@nvidia.com> <20190201033621.16814-3-josephl@nvidia.com> <9370a0e4-2c76-6e9e-9219-121f92cdb14a@gmail.com> <46a1a62f-29b1-caac-ba68-e1394a76b3af@gmail.com> <85988378-0c88-6b71-00df-0700a7b4cdf7@nvidia.com> <4c89fd38-eacd-4643-52d3-da4760ecb4c5@nvidia.com> <57549882-4d0a-64ac-da04-7e790ac2d80e@gmail.com> <9437d5b5-5af0-9393-169c-2ebaf384c75c@nvidia.com> From: Dmitry Osipenko Message-ID: <3d173ddf-46d2-165c-7886-cea685a0737d@gmail.com> Date: Sat, 2 Feb 2019 16:30:38 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <9437d5b5-5af0-9393-169c-2ebaf384c75c@nvidia.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 01.02.2019 18:37, Joseph Lo пишет: > On 2/1/19 11:13 PM, Dmitry Osipenko wrote: >> 01.02.2019 17:13, Joseph Lo пишет: >>> On 2/1/19 9:54 PM, Jon Hunter wrote: >>>> >>>> On 01/02/2019 13:11, Dmitry Osipenko wrote: >>>>> 01.02.2019 16:06, Dmitry Osipenko пишет: >>>>>> 01.02.2019 6:36, Joseph Lo пишет: >>>>>>> Add support for the Tegra210 timer that runs at oscillator clock >>>>>>> (TMR10-TMR13). We need these timers to work as clock event device and to >>>>>>> replace the ARMv8 architected timer due to it can't survive across the >>>>>>> power cycle of the CPU core or CPUPORESET signal. So it can't be a wake-up >>>>>>> source when CPU suspends in power down state. >>>>>>> >>>>>>> Also convert the original driver to use timer-of API. >>>>>>> >>>>>>> Cc: Daniel Lezcano >>>>>>> Cc: Thomas Gleixner >>>>>>> Cc: linux-kernel@vger.kernel.org >>>>>>> Signed-off-by: Joseph Lo >>>>>>> Acked-by: Thierry Reding >>>>>>> --- > snip. >>>>>>> +} >>>>>>> +TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_timer_init); >>>>>>> +#else /* CONFIG_ARM */ >>>>>>> +static int __init tegra20_init_timer(struct device_node *np) >>>>>>> +{ >>>>>> What about T132? Isn't it ARM64 which uses tegra20-timer IP? At least T132 DT suggests so and seems this change will break it. >>>>>> >>>>>> [snip] >>>>>> >>>>> >>>>> Ah, noticed the "depends on ARM" in Kconfig.. Seems okay then. >>>>> >>>> >>>> >>>> This is a good point, because even though we had 'depends on ARM', this >>>> still means that the Tegra132 DT is incorrect. >>>> >>>> Joseph, can you take a quick look at Tegra132? >>> >>> Hi Jon and Dmitry, >>> >>> No worry about T132, T132 uses arch timer (v7). The tegra20 timer driver has never been used. We should fix the dtsi file later. >> >> Hi Joseph, >> >> So is T132 HW actually incompatible with the tegra20-timer? If it's compatible, then I think the driver's code should be made more universal to support T132. >> > > From HW point of view, the TIMER1 ~ TIMER4 is compatible with "nvidia,tegra20-timer". But Tegra132 actually has 10 timers which are exactly the same as Tegra30. So it should backward compatible with "nvidia,tegra30-timer", which is tegra_wdt driver now. And Tegra132 should never use this driver. Then shouldn't device tree look like this? Why TMR7-TMR0 are not defined there? timer@60005000 { compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer"; reg = <0x0 0x60005000 0x0 0x400>; interrupts = , , , , , ; ; ; ; ; clocks = <&tegra_car TEGRA124_CLK_TIMER>; clock-names = "timer"; }; TMR 0,6,7,8,9 should define a shared interrupt as well, but seems the shared interrupt provider is not supported in upstream. Also note that seems T124/132 device tree has a typo (I'm looking at TK1 TRM), TMR6 IRQ is 152 and not 122. And T30 device tree looks incorrect, TRM says that TMR1-TMR5 have a "dedicated interrupt bit", but not TMR6.