From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from sg-1-30.ptr.blmpb.com (sg-1-30.ptr.blmpb.com [118.26.132.30]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBEF528A714 for ; Wed, 6 Aug 2025 10:19:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=118.26.132.30 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754475546; cv=none; b=mHt1LrvlxD3mGSvfIFl9Fmkc4RExV9QUP53iIdG0tfaKidvU5Zebw5KEtsPvqdvYJbEJepGzV25muRhPlDF/6VGqdl6/+3M5wlwdKD5P4ov4ZWLVxqEqsd4NjBfRNc0OTJK4GTIiLciPCSPnVjQEEAACTP3bbFnEMtbQyHx0tAc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754475546; c=relaxed/simple; bh=B6sQ1NetsPTmtFsLdHDYYBU+L1q12bILqn6b3beWkGs=; h=Cc:From:To:Date:Message-Id:In-Reply-To:Content-Type:Subject: Mime-Version:References; b=jIOwlG6XJCSOrmxyjZx8F6Pk+HBRlLl+sRWepr8eLar95DXRbAMKx51/nQ8c/cN5YNcAZbUJQfS/Cyk6Z+Kxg5S7h7cZl93zay1TAuQhaMdVJ1gfHK4mxp2M1jdl7OEGUJXYA0VNxW6t4AkEEl4AWwNcG/oj9xt1X88JVnrsmU4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=lanxincomputing.com; spf=pass smtp.mailfrom=lanxincomputing.com; dkim=pass (2048-bit key) header.d=lanxincomputing-com.20200927.dkim.feishu.cn header.i=@lanxincomputing-com.20200927.dkim.feishu.cn header.b=TXTmBTe3; arc=none smtp.client-ip=118.26.132.30 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=lanxincomputing.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=lanxincomputing.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=lanxincomputing-com.20200927.dkim.feishu.cn header.i=@lanxincomputing-com.20200927.dkim.feishu.cn header.b="TXTmBTe3" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=s1; d=lanxincomputing-com.20200927.dkim.feishu.cn; t=1754474707; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=HAuif9gFjp03a1ED0sRYhN2Xh+Oo5vYjt6vdU6y4qaw=; b=TXTmBTe33mszmANQficYSPl82udgMtn/ERcp3bvHMULbkLB+iKJfuYQ8Q9FGac5AsEtR3a K6GACDuM8lcDfkiBMHfyQQoKdWjXI5NIT5F97VfnNr30VqCHY5P8N7o6h2KNb4uES9KOGj U9CqhvjdIKvBrxBpFkKLP90Or0vwvgWWuclFafJol5k9B2fnfVwOstmjHY0L6faXSTamF5 wVIa2GXEHx0Nn7QYYwPCeIB55n7qgThSfM7PPoehSYdD2hRCXqqAj9PC9uCnEhqfyGGOFh hIDEoQzMGvWqmsVPmct0tQmOGBvQIjcNAHSxhgetQwUmToDE1mnMZDQztODsHw== Cc: , , , "Anup Patel" , "Atish Patra" , "Paul Walmsley" , "Palmer Dabbelt" , "Albert Ou" , "Alexandre Ghiti" , "Daniel Henrique Barboza" , From: "Nutty Liu" To: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Date: Wed, 6 Aug 2025 18:05:02 +0800 Message-Id: <3d7df3b0-27c5-47a2-a4a1-dde168e7848e@lanxincomputing.com> X-Lms-Return-Path: In-Reply-To: <20250805104418.196023-4-rkrcmar@ventanamicro.com> Content-Transfer-Encoding: quoted-printable Received: from [127.0.0.1] ([116.237.111.137]) by smtp.feishu.cn with ESMTPS; Wed, 06 Aug 2025 18:05:03 +0800 Content-Type: text/plain; charset=UTF-8 User-Agent: Mozilla Thunderbird Content-Language: en-US Subject: Re: [PATCH] RISC-V: KVM: fix stack overrun when loading vlenb Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250805104418.196023-4-rkrcmar@ventanamicro.com> X-Original-From: Nutty Liu On 8/5/2025 6:44 PM, Radim Kr=C4=8Dm=C3=A1=C5=99 wrote: > The userspace load can put up to 2048 bits into an xlen bit stack > buffer. We want only xlen bits, so check the size beforehand. > > Fixes: 2fa290372dfe ("RISC-V: KVM: add 'vlenb' Vector CSR") > Cc: > Signed-off-by: Radim Kr=C4=8Dm=C3=A1=C5=99 > --- Reviewed-by: Nutty Liu Thanks, Nutty > arch/riscv/kvm/vcpu_vector.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/riscv/kvm/vcpu_vector.c b/arch/riscv/kvm/vcpu_vector.c > index a5f88cb717f3..05f3cc2d8e31 100644 > --- a/arch/riscv/kvm/vcpu_vector.c > +++ b/arch/riscv/kvm/vcpu_vector.c > @@ -182,6 +182,8 @@ int kvm_riscv_vcpu_set_reg_vector(struct kvm_vcpu *vc= pu, > struct kvm_cpu_context *cntx =3D &vcpu->arch.guest_context; > unsigned long reg_val; > =20 > + if (reg_size !=3D sizeof(reg_val)) > + return -EINVAL; > if (copy_from_user(®_val, uaddr, reg_size)) > return -EFAULT; > if (reg_val !=3D cntx->vector.vlenb)