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McKenney" , Arnd Bergmann , Palmer Dabbelt , Mark Rutland , Will Deacon , Peter Zijlstra , linux-arch , Linux Kernel Mailing List , linux-riscv , Guo Ren References: <20220412034957.1481088-1-guoren@kernel.org> From: Dan Lustig In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-ClientProxiedBy: BL1PR13CA0398.namprd13.prod.outlook.com (2603:10b6:208:2c2::13) To MN2PR12MB3437.namprd12.prod.outlook.com (2603:10b6:208:c3::20) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 05564653-418d-4ebd-9a95-08da2227cd94 X-MS-TrafficTypeDiagnostic: MW2PR12MB2410:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: YLjb9UhexdN5E2Vc2QZHKZNlOE3nqlOPIOdBZLDEamHeZ/OkoxcK8BwkgbItVCcIJkIxGA3VXLm/Vdeeijaa5id4jHaIoa2PXi+NXl4vtRTp9LkUBTknOkZbar+UsZS9oYyueEvBshDJ396SHl63RjnVpqItQlNe9GE8VS8FXaP14D9qRAjI7+hSd3p8RChBcf7ypgDQy42Df4qgcZdrt71ckHpTZVt7ISWfunufHAH2sPufP6Z/jntlBXb8KuMlpXrI8J5ri7sDNPdsxMCY0pepxceM+dnYyCszRzWU/66Sm6TADM37Q8tVMPE9h52gx+J842WafZxmBYmtSToQLahZWuR26btCBYZFw2MfOD/NZ37Yyayb51fl211iNi+j2mgOfikp9qni7bierDiCWZ3aGFOdpGcAxOuEpQW0RcJ3jy6IX/YyDpFtUb9S/SYFJ8A5TLXvNgzddYSHNTGKVEjho844P8+1lkoAc4gRFeOhEnuqisjobngcdODjTX5V6RWwGfT7H+cPgBpC8NLQSHE6JyFRS4cGxUICYjssGDqI0bA7fV33lJ5VlzMn8V5teVfpTjKz+GmdawzFt0B96Yyt3pY/T9KRBScPMmBCf/WoozjeaAPwio5xP6sjymhuA4wekBUtvv+Gr2kpqNb0vMqHAqDY0CWm0jczsMBPOu64UjbWZaHVVkadnsI8oymYdNkWqZVM6Yqj3fF3COy1ZNU+89qsIFQaYW1D5/SEC+fboQdlpQTdEh6AYAe9Y+H8 X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MN2PR12MB3437.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230001)(4636009)(366004)(2616005)(66476007)(110136005)(26005)(6512007)(186003)(5660300002)(6486002)(8676002)(66946007)(4326008)(508600001)(31696002)(86362001)(316002)(7416002)(66556008)(38100700002)(6666004)(6506007)(54906003)(31686004)(36756003)(83380400001)(2906002)(8936002)(53546011)(45980500001)(43740500002);DIR:OUT;SFP:1101; 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For example, can > From the RVWMO spec description, the .aqrl annotation appends the same > effect with "fence rw, rw" to the AMO instruction, so it's RCsc. > > Not only .aqrl, and I think the below also could be an RCsc when > sc.w.aq is executed: > A: Pre-Access > B: lr.w.rl ADDR-0 > ... > C: sc.w.aq ADDR-0 > D: Post-Acess > Because sc.w.aq has overlap address & data dependency on lr.w.rl, the > global memory order should be A->B->C->D when sc.w.aq is executed. For > the amoswap These opcodes aren't actually meaningful, unfortunately. Quoting the ISA manual chapter 10.2: "Software should not set the rl bit on an LR instruction unless the aq bit is also set, nor should software set the aq bit on an SC instruction unless the rl bit is also set." Dan > The purpose of the whole patchset is to reduce the usage of > independent fence rw, rw instructions, and maximize the usage of the > .aq/.rl/.aqrl aonntation of RISC-V. > > __asm__ __volatile__ ( \ > "0: lr.w %0, %2\n" \ > " bne %0, %z3, 1f\n" \ > " sc.w.rl %1, %z4, %2\n" \ > " bnez %1, 0b\n" \ > " fence rw, rw\n" \ > "1:\n" \ > >> we end up with u == 1, v == 1, r1 on P0 is 0 and r1 on P1 is 0, for the >> following litmus test? >> >> C lr-sc-aqrl-pair-vs-full-barrier >> >> {} >> >> P0(int *x, int *y, atomic_t *u) >> { >> int r0; >> int r1; >> >> WRITE_ONCE(*x, 1); >> r0 = atomic_cmpxchg(u, 0, 1); >> r1 = READ_ONCE(*y); >> } >> >> P1(int *x, int *y, atomic_t *v) >> { >> int r0; >> int r1; >> >> WRITE_ONCE(*y, 1); >> r0 = atomic_cmpxchg(v, 0, 1); >> r1 = READ_ONCE(*x); >> } >> >> exists (u=1 /\ v=1 /\ 0:r1=0 /\ 1:r1=0) > I think my patchset won't affect the above sequence guarantee. Current > RISC-V implementation only gives RCsc when the original value is the > same at least once. So I prefer RISC-V cmpxchg should be: > > > - "0: lr.w %0, %2\n" \ > + "0: lr.w.rl %0, %2\n" \ > " bne %0, %z3, 1f\n" \ > " sc.w.rl %1, %z4, %2\n" \ > " bnez %1, 0b\n" \ > - " fence rw, rw\n" \ > "1:\n" \ > + " fence w, rw\n" \ > > To give an unconditional RSsc for atomic_cmpxchg. > >> >> Regards, >> Boqun > > >