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Sun, 27 Apr 2025 20:27:01 -0700 (PDT) Message-ID: <40232d5ef59383dc44fd8b91dbc2b0ba71f1d84f.camel@gmail.com> Subject: Re: [PATCH v4 3/3] PCI: dw-rockchip: Unify link status checks with FIELD_GET From: Wilfred Mallawa To: Hans Zhang <18255117159@163.com>, lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, heiko@sntech.de Cc: manivannan.sadhasivam@linaro.org, robh@kernel.org, jingoohan1@gmail.com, shawn.lin@rock-chips.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Niklas Cassel Date: Mon, 28 Apr 2025 13:26:54 +1000 In-Reply-To: <20250427125316.99627-4-18255117159@163.com> References: <20250427125316.99627-1-18255117159@163.com> <20250427125316.99627-4-18255117159@163.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.54.3 (3.54.3-1.fc41) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Sun, 2025-04-27 at 20:53 +0800, Hans Zhang wrote: > Link-up detection manually checked PCIE_LINKUP bits across RC/EP > modes, > leading to code duplication. Centralize the logic using FIELD_GET. > This > removes redundancy and abstracts hardware-specific bit masking, > ensuring > consistent link state handling. >=20 > Signed-off-by: Hans Zhang <18255117159@163.com> > Reviewed-by: Niklas Cassel > Reviewed-by: Manivannan Sadhasivam > --- > =C2=A0drivers/pci/controller/dwc/pcie-dw-rockchip.c | 21 +++++++---------= - > -- > =C2=A01 file changed, 8 insertions(+), 13 deletions(-) >=20 > diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c > b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > index a778f4f61595..bfc47dab32e5 100644 > --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c > +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > @@ -8,6 +8,7 @@ > =C2=A0 * Author: Simon Xue > =C2=A0 */ > =C2=A0 > +#include > =C2=A0#include > =C2=A0#include > =C2=A0#include > @@ -60,9 +61,8 @@ > =C2=A0 > =C2=A0/* LTSSM Status Register */ > =C2=A0#define PCIE_CLIENT_LTSSM_STATUS 0x300 > -#define=C2=A0 PCIE_SMLH_LINKUP BIT(16) > -#define=C2=A0 PCIE_RDLH_LINKUP BIT(17) > -#define=C2=A0 PCIE_LINKUP (PCIE_SMLH_LINKUP | > PCIE_RDLH_LINKUP) > +#define=C2=A0 PCIE_LINKUP 0x3 > +#define=C2=A0 PCIE_LINKUP_MASK GENMASK(17, 16) > =C2=A0#define=C2=A0 PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) > =C2=A0 > =C2=A0struct rockchip_pcie { > @@ -188,10 +188,7 @@ static int rockchip_pcie_link_up(struct dw_pcie > *pci) > =C2=A0 struct rockchip_pcie *rockchip =3D to_rockchip_pcie(pci); > =C2=A0 u32 val =3D rockchip_pcie_get_ltssm(rockchip); > =C2=A0 > - if ((val & PCIE_LINKUP) =3D=3D PCIE_LINKUP) > - return 1; > - > - return 0; > + return FIELD_GET(PCIE_LINKUP_MASK, val) =3D=3D PCIE_LINKUP; > =C2=A0} > =C2=A0 > =C2=A0static void rockchip_pcie_enable_l0s(struct dw_pcie *pci) > @@ -450,7 +447,7 @@ static irqreturn_t > rockchip_pcie_rc_sys_irq_thread(int irq, void *arg) > =C2=A0 struct dw_pcie *pci =3D &rockchip->pci; > =C2=A0 struct dw_pcie_rp *pp =3D &pci->pp; > =C2=A0 struct device *dev =3D pci->dev; > - u32 reg, val; > + u32 reg; > =C2=A0 > =C2=A0 reg =3D rockchip_pcie_readl_apb(rockchip, > PCIE_CLIENT_INTR_STATUS_MISC); > =C2=A0 rockchip_pcie_writel_apb(rockchip, reg, > PCIE_CLIENT_INTR_STATUS_MISC); > @@ -459,8 +456,7 @@ static irqreturn_t > rockchip_pcie_rc_sys_irq_thread(int irq, void *arg) > =C2=A0 dev_dbg(dev, "LTSSM_STATUS: %#x\n", > rockchip_pcie_get_ltssm(rockchip)); > =C2=A0 > =C2=A0 if (reg & PCIE_RDLH_LINK_UP_CHGED) { > - val =3D rockchip_pcie_get_ltssm(rockchip); > - if ((val & PCIE_LINKUP) =3D=3D PCIE_LINKUP) { > + if (rockchip_pcie_link_up(pci)) { > =C2=A0 dev_dbg(dev, "Received Link up event. > Starting enumeration!\n"); > =C2=A0 /* Rescan the bus to enumerate endpoint > devices */ > =C2=A0 pci_lock_rescan_remove(); > @@ -477,7 +473,7 @@ static irqreturn_t > rockchip_pcie_ep_sys_irq_thread(int irq, void *arg) > =C2=A0 struct rockchip_pcie *rockchip =3D arg; > =C2=A0 struct dw_pcie *pci =3D &rockchip->pci; > =C2=A0 struct device *dev =3D pci->dev; > - u32 reg, val; > + u32 reg; > =C2=A0 > =C2=A0 reg =3D rockchip_pcie_readl_apb(rockchip, > PCIE_CLIENT_INTR_STATUS_MISC); > =C2=A0 rockchip_pcie_writel_apb(rockchip, reg, > PCIE_CLIENT_INTR_STATUS_MISC); > @@ -491,8 +487,7 @@ static irqreturn_t > rockchip_pcie_ep_sys_irq_thread(int irq, void *arg) > =C2=A0 } > =C2=A0 > =C2=A0 if (reg & PCIE_RDLH_LINK_UP_CHGED) { > - val =3D rockchip_pcie_get_ltssm(rockchip); > - if ((val & PCIE_LINKUP) =3D=3D PCIE_LINKUP) { > + if (rockchip_pcie_link_up(pci)) { > =C2=A0 dev_dbg(dev, "link up\n"); > =C2=A0 dw_pcie_ep_linkup(&pci->ep); > =C2=A0 } Reviewed-by: Wilfred Mallawa