From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB683C433EF for ; Wed, 13 Oct 2021 08:57:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BD74A61074 for ; Wed, 13 Oct 2021 08:57:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238937AbhJMI7v (ORCPT ); Wed, 13 Oct 2021 04:59:51 -0400 Received: from gloria.sntech.de ([185.11.138.130]:43368 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229987AbhJMI7u (ORCPT ); Wed, 13 Oct 2021 04:59:50 -0400 Received: from ip5f5a6e92.dynamic.kabel-deutschland.de ([95.90.110.146] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1maa4z-0003gQ-6C; Wed, 13 Oct 2021 10:57:41 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Guo Ren , Anup Patel Cc: Atish Patra , Marc Zyngier , Thomas Gleixner , Palmer Dabbelt , "linux-kernel@vger.kernel.org List" , linux-riscv , Guo Ren , Rob Herring , Palmer Dabbelt Subject: Re: [PATCH V3 1/2] dt-bindings: update riscv plic compatible string Date: Wed, 13 Oct 2021 10:57:40 +0200 Message-ID: <4039032.XOxOlHldtI@diego> In-Reply-To: References: <20211013012149.2834212-1-guoren@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Anup, Am Mittwoch, 13. Oktober 2021, 07:11:46 CEST schrieb Anup Patel: > On Wed, Oct 13, 2021 at 6:52 AM wrote: > > > > From: Guo Ren > > > > Add the compatible string "thead,c900-plic" to the riscv plic > > bindings to support SOCs with thead,c9xx processor cores. > > > > Signed-off-by: Guo Ren > > Cc: Rob Herring > > Cc: Palmer Dabbelt > > Cc: Anup Patel > > Cc: Atish Patra > > > > --- > > > > Changes since V3: > > - Rename "c9xx" to "c900" > > - Add thead,c900-plic in the description section > > --- > > .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 6 ++++++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > > index 08d5a57ce00f..82629832e5a5 100644 > > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > > @@ -35,6 +35,11 @@ description: > > contains a specific memory layout, which is documented in chapter 8 of the > > SiFive U5 Coreplex Series Manual . > > > > + While the "thead,c900-plic" would mask IRQ with readl(claim), so it needn't > > + mask/unmask which needed in RISC-V PLIC. When in IRQS_ONESHOT & IRQCHIP_EOI_THREADED > > + path, unnecessary mask operation would cause a blocking irq bug in thead,c900-plic. > > + Because when IRQ is disabled in c900, writel(hwirq, claim) would be invalid. > > This is a totally incorrect description of the errata required for C9xx PLIC. > > Please don't project non-compliance as a feature of C9xx PLIC. > > > + > > maintainers: > > - Sagar Kadam > > - Paul Walmsley > > @@ -46,6 +51,7 @@ properties: > > - enum: > > - sifive,fu540-c000-plic > > - canaan,k210-plic > > + - thead,c900-plic we still want specific SoC names in the compatible, the "c900" is still a sort-of placeholder. > > - const: sifive,plic-1.0.0 > > The PLIC DT node requires two compatible string: > , > > The C9xx PLIC is not RISC-V PLIC so, the DT node should > be: "thead,c900-plic", "thead,c9xx-plic" > > You need to change "- const: sifive,plic-1.0.0" to > - enum: > - sifive,plic-1.0.0 > - thead,c9xx-plic