Re: Why no interrupt priorities?

Michael Frank
2004-02-27T19:12:51Z

On Fri, 27 Feb 2004 13:15:40 -0500, Chris Friesen <cfriesen@nortelnetworks.com> wrote:

> Grover, Andrew wrote:
>
>> If a device later in the handler chain is also interrupting, then the
>> interrupt will immediately trigger again. The irq line will remain
>> asserted until nobody is asserting it.
>
> I thought I saw examples of edge-triggered shared interrupts earlier in
> the thread. Doesn't that give the reason for this behaviour?

To make it more clear

/---active--~--\
IRQa ---------/ \-------------------------

/-------------------------
IRQb ----------------------~--/

/----------~--\/\/-----------------------
IRQBUS ---------/

Program ....Main.....|.ISR...........|.Main............
Flow Edge trig Interrupt _dead_

Program ....Main.....|.ISR...........|.Main.|ISR.....
Flow Level trig

When IRQBUS is level triggered, ISR is reeentered fairly quickly
(within one instruction) after IRET (depends on CPU).

The only way to "fix" edge-trig shared IRQ's is to

a) perform blind extra poll of the _entire_ chain until _no_ devices
were serviced
b) Check IRQBUS and poll _entire_ chain when active.

And I find it mind boggling that IRQ's other than Timer and RTC are
edge triggered which also explains the troubles with sharing IRQ's.

It would be better to just program them level.

I good rule is:

An IRQ should be edge triggered when the ISR has no influence on the
state of the IRQ line. This is usually the case with periodic signals
such as timer outputs or strobes by rotary encoders and the like.

All other IRQs - in particular those "reset" by a software generated
events such as reading or writing a register - should be level triggered.

Regards
Michael