From: Manfred Spraul <manfred@colorfullife.com>
To: Terence Ripperda <tripperda@nvidia.com>
Cc: linux-kernel@vger.kernel.org
Subject: Re: PAT support
Date: Tue, 13 Apr 2004 07:34:22 +0200 [thread overview]
Message-ID: <407B7BDE.5030002@colorfullife.com> (raw)
Hi Terence,
in your patch, you write
+/* Here is the PAT's default layout on ia32 cpus when we are done.
+ * PAT0: Write Back
+ * PAT1: Write Combine
+ * PAT2: Uncached
+ * PAT3: Uncacheable
+ * PAT4: Write Through
+ * PAT5: Write Protect
+ * PAT6: Uncached
+ * PAT7: Uncacheable
Is that layout possible?
There is an errata in the B2 and C1 stepping of the Pentium 4 cpus that
results in incorrect PAT numbers: the highest bit is ignored by the CPU
under some circumstances. There's a similar errata (E27) that affects
all Pentium 3 cpus: The highest bit is always ignored.
I think we need a fallback to 4 PAT entries.
--
Manfred
next reply other threads:[~2004-04-13 5:34 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-04-13 5:34 Manfred Spraul [this message]
2004-04-13 14:02 ` PAT support Pavel Machek
2004-04-13 16:40 ` Terence Ripperda
2004-04-15 4:05 ` Eric W. Biederman
-- strict thread matches above, loose matches on Subject: below --
2004-04-15 21:38 Albert Cahalan
[not found] <1KifY-uA-7@gated-at.bofh.it>
2004-04-13 0:01 ` Andi Kleen
2004-04-13 16:21 ` Terence Ripperda
2004-04-14 0:58 ` Andi Kleen
2004-04-16 18:07 ` Terence Ripperda
2004-04-17 0:42 ` Andi Kleen
2004-04-19 22:54 ` Terence Ripperda
2004-04-20 18:51 ` Andi Kleen
2004-04-21 23:19 ` Terence Ripperda
2004-04-22 4:21 ` Andi Kleen
2004-04-15 4:11 ` Eric W. Biederman
2004-04-15 16:38 ` Andi Kleen
2004-04-15 18:39 ` Eric W. Biederman
2004-04-12 22:29 Terence Ripperda
2004-04-13 8:36 ` Andy Whitcroft
2004-04-13 16:50 ` Terence Ripperda
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