* [PATCH v2 1/4] clk: hisilicon: Add helper functions for platform driver
2023-03-29 7:50 [PATCH v2 0/4] clk: hisilicon: Migrate devm APIs David Yang
@ 2023-03-29 7:50 ` David Yang
2023-04-05 19:51 ` Stephen Boyd
2023-03-29 7:50 ` [PATCH v2 2/4] clk: hisilicon: Use helper functions David Yang
` (3 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: David Yang @ 2023-03-29 7:50 UTC (permalink / raw)
To: linux-clk; +Cc: David Yang, Michael Turquette, Stephen Boyd, linux-kernel
Helper functions extract common operations on platform drivers.
During migration to devm APIs, (virtual) fixed clocks were found hard on
devm APIs, since they often depended by crucial peripherals, thus require
early initialization before device probing, and cannot use devm APIs.
One solution to this problem is to add a "fixed-clock" node to device tree,
independent to clock device, and make those peripherals depend on that.
However, there is also some devices that do use fixed clocks provided by
drivers, for example clk-hi3660.c .
To simplify codes, we migrate clocks of other types to devm APIs, while
keep fixed clocks self-managed, alongside with struct hisi_clock_data, and
remove devm-managed hisi_clock_data.
`hisi_clk_alloc` will be removed in the following patch.
Signed-off-by: David Yang <mmyangfl@gmail.com>
---
drivers/clk/hisilicon/clk.c | 148 ++++++++++++++++++++++++++++++++++
drivers/clk/hisilicon/clk.h | 56 +++++++++++--
drivers/clk/hisilicon/crg.h | 5 ++
drivers/clk/hisilicon/reset.c | 47 ++++++++++-
4 files changed, 248 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c
index 54d9fdc93599..96bbc09e7d45 100644
--- a/drivers/clk/hisilicon/clk.c
+++ b/drivers/clk/hisilicon/clk.c
@@ -88,6 +88,25 @@ struct hisi_clock_data *hisi_clk_init(struct device_node *np,
}
EXPORT_SYMBOL_GPL(hisi_clk_init);
+void hisi_clk_free(struct device_node *np, struct hisi_clock_data *data)
+{
+ if (data->clks) {
+ if (data->clks->fixed_rate_clks_num)
+ hisi_clk_unregister_fixed_rate(data->clks->fixed_rate_clks,
+ data->clks->fixed_rate_clks_num,
+ data);
+ if (data->clks->fixed_factor_clks_num)
+ hisi_clk_unregister_fixed_factor(data->clks->fixed_factor_clks,
+ data->clks->fixed_factor_clks_num,
+ data);
+ }
+
+ of_clk_del_provider(np);
+ kfree(data->clk_data.clks);
+ kfree(data);
+}
+EXPORT_SYMBOL_GPL(hisi_clk_free);
+
int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *clks,
int nums, struct hisi_clock_data *data)
{
@@ -341,3 +360,132 @@ void __init hi6220_clk_register_divider(const struct hi6220_divider_clock *clks,
data->clk_data.clks[clks[i].id] = clk;
}
}
+
+int hisi_clk_register(struct device *dev, const struct hisi_clocks *clks,
+ struct hisi_clock_data *data)
+{
+ int ret;
+
+ if (clks->mux_clks_num) {
+ ret = hisi_clk_register_mux(clks->mux_clks,
+ clks->mux_clks_num, data);
+ if (ret)
+ return ret;
+ }
+
+ if (clks->phase_clks_num) {
+ ret = hisi_clk_register_phase(dev, clks->phase_clks,
+ clks->phase_clks_num, data);
+ if (ret)
+ return ret;
+ }
+
+ if (clks->divider_clks_num) {
+ ret = hisi_clk_register_divider(clks->divider_clks,
+ clks->divider_clks_num, data);
+ if (ret)
+ return ret;
+ }
+
+ if (clks->gate_clks_num) {
+ ret = hisi_clk_register_gate(clks->gate_clks,
+ clks->gate_clks_num, data);
+ if (ret)
+ return ret;
+ }
+
+ if (clks->gate_sep_clks_num) {
+ hisi_clk_register_gate_sep(clks->gate_sep_clks,
+ clks->gate_sep_clks_num, data);
+ }
+
+ if (clks->clk_register_customized && clks->customized_clks_num) {
+ ret = clks->clk_register_customized(dev, clks->customized_clks,
+ clks->customized_clks_num, data);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(hisi_clk_register);
+
+int hisi_clk_early_init(struct device_node *np, const struct hisi_clocks *clks)
+{
+ struct hisi_clock_data *data;
+ int ret;
+
+ data = hisi_clk_init(np, clks->nr);
+ if (!data)
+ return -ENOMEM;
+ data->clks = clks;
+
+ ret = hisi_clk_register_fixed_rate(clks->fixed_rate_clks,
+ clks->fixed_rate_clks_num, data);
+ if (ret)
+ goto err;
+
+ ret = hisi_clk_register_fixed_factor(clks->fixed_factor_clks,
+ clks->fixed_factor_clks_num, data);
+ if (ret)
+ goto err;
+
+ np->data = data;
+ return 0;
+
+err:
+ hisi_clk_free(np, data);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(hisi_clk_early_init);
+
+int hisi_clk_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ const struct hisi_clocks *clks;
+ struct hisi_clock_data *data;
+ int ret;
+
+ clks = of_device_get_match_data(dev);
+ if (!clks)
+ return -ENOENT;
+
+ if (!np->data) {
+ ret = hisi_clk_early_init(np, clks);
+ if (ret)
+ return ret;
+ }
+
+ data = np->data;
+ np->data = NULL;
+
+ if (clks->prologue) {
+ ret = clks->prologue(dev, data);
+ if (ret)
+ goto err;
+ }
+
+ ret = hisi_clk_register(dev, clks, data);
+ if (ret)
+ goto err;
+
+ platform_set_drvdata(pdev, data);
+ return 0;
+
+err:
+ hisi_clk_free(np, data);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(hisi_clk_probe);
+
+int hisi_clk_remove(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct hisi_clock_data *data = platform_get_drvdata(pdev);
+
+ hisi_clk_free(np, data);
+ return 0;
+}
+EXPORT_SYMBOL_GPL(hisi_clk_remove);
diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h
index 7a9b42e1b027..def94498e14d 100644
--- a/drivers/clk/hisilicon/clk.h
+++ b/drivers/clk/hisilicon/clk.h
@@ -17,10 +17,12 @@
#include <linux/spinlock.h>
struct platform_device;
+struct hisi_clocks;
struct hisi_clock_data {
struct clk_onecell_data clk_data;
void __iomem *base;
+ const struct hisi_clocks *clks;
};
struct hisi_fixed_rate_clock {
@@ -103,6 +105,38 @@ struct hisi_gate_clock {
const char *alias;
};
+struct hisi_clocks {
+ int nr;
+
+ int (*prologue)(struct device *dev, struct hisi_clock_data *data);
+
+ const struct hisi_fixed_rate_clock *fixed_rate_clks;
+ int fixed_rate_clks_num;
+
+ const struct hisi_fixed_factor_clock *fixed_factor_clks;
+ int fixed_factor_clks_num;
+
+ const struct hisi_mux_clock *mux_clks;
+ int mux_clks_num;
+
+ const struct hisi_phase_clock *phase_clks;
+ int phase_clks_num;
+
+ const struct hisi_divider_clock *divider_clks;
+ int divider_clks_num;
+
+ const struct hisi_gate_clock *gate_clks;
+ int gate_clks_num;
+
+ const struct hisi_gate_clock *gate_sep_clks;
+ int gate_sep_clks_num;
+
+ const void *customized_clks;
+ int customized_clks_num;
+ int (*clk_register_customized)(struct device *dev, const void *clks,
+ int num, struct hisi_clock_data *data);
+};
+
struct clk *hisi_register_clkgate_sep(struct device *, const char *,
const char *, unsigned long,
void __iomem *, u8,
@@ -113,6 +147,7 @@ struct clk *hi6220_register_clkdiv(struct device *dev, const char *name,
struct hisi_clock_data *hisi_clk_alloc(struct platform_device *, int);
struct hisi_clock_data *hisi_clk_init(struct device_node *, int);
+void hisi_clk_free(struct device_node *np, struct hisi_clock_data *data);
int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *,
int, struct hisi_clock_data *);
int hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *,
@@ -134,7 +169,16 @@ void hisi_clk_register_gate_sep(const struct hisi_gate_clock *,
void hi6220_clk_register_divider(const struct hi6220_divider_clock *,
int, struct hisi_clock_data *);
-#define hisi_clk_unregister(type) \
+int hisi_clk_register(struct device *dev, const struct hisi_clocks *clks,
+ struct hisi_clock_data *data);
+
+/* helper functions for platform driver */
+
+int hisi_clk_early_init(struct device_node *np, const struct hisi_clocks *clks);
+int hisi_clk_probe(struct platform_device *pdev);
+int hisi_clk_remove(struct platform_device *pdev);
+
+#define hisi_clk_unregister_fn(type) \
static inline \
void hisi_clk_unregister_##type(const struct hisi_##type##_clock *clks, \
int nums, struct hisi_clock_data *data) \
@@ -148,10 +192,10 @@ void hisi_clk_unregister_##type(const struct hisi_##type##_clock *clks, \
} \
}
-hisi_clk_unregister(fixed_rate)
-hisi_clk_unregister(fixed_factor)
-hisi_clk_unregister(mux)
-hisi_clk_unregister(divider)
-hisi_clk_unregister(gate)
+hisi_clk_unregister_fn(fixed_rate)
+hisi_clk_unregister_fn(fixed_factor)
+hisi_clk_unregister_fn(mux)
+hisi_clk_unregister_fn(divider)
+hisi_clk_unregister_fn(gate)
#endif /* __HISI_CLK_H */
diff --git a/drivers/clk/hisilicon/crg.h b/drivers/clk/hisilicon/crg.h
index 803f6ba6d7a2..d9544f1f2625 100644
--- a/drivers/clk/hisilicon/crg.h
+++ b/drivers/clk/hisilicon/crg.h
@@ -22,4 +22,9 @@ struct hisi_crg_dev {
const struct hisi_crg_funcs *funcs;
};
+/* helper functions for platform driver */
+
+int hisi_crg_probe(struct platform_device *pdev);
+int hisi_crg_remove(struct platform_device *pdev);
+
#endif /* __HISI_CRG_H */
diff --git a/drivers/clk/hisilicon/reset.c b/drivers/clk/hisilicon/reset.c
index 93cee17db8b1..3464e3b4d708 100644
--- a/drivers/clk/hisilicon/reset.c
+++ b/drivers/clk/hisilicon/reset.c
@@ -5,12 +5,16 @@
* Copyright (c) 2015-2016 HiSilicon Technologies Co., Ltd.
*/
+#include <linux/device.h>
#include <linux/io.h>
+#include <linux/kernel.h>
#include <linux/of_address.h>
-#include <linux/platform_device.h>
+#include <linux/of_device.h>
#include <linux/reset-controller.h>
-#include <linux/slab.h>
#include <linux/spinlock.h>
+
+#include "clk.h"
+#include "crg.h"
#include "reset.h"
#define HISI_RESET_BIT_MASK 0x1f
@@ -116,3 +120,42 @@ void hisi_reset_exit(struct hisi_reset_controller *rstc)
reset_controller_unregister(&rstc->rcdev);
}
EXPORT_SYMBOL_GPL(hisi_reset_exit);
+
+int hisi_crg_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct hisi_crg_dev *crg;
+ int ret;
+
+ crg = devm_kmalloc(dev, sizeof(*crg), GFP_KERNEL);
+ if (!crg)
+ return -ENOMEM;
+
+ ret = hisi_clk_probe(pdev);
+ if (ret)
+ return ret;
+
+ crg->rstc = hisi_reset_init(pdev);
+ if (!crg->rstc) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ platform_set_drvdata(pdev, crg);
+ return 0;
+
+err:
+ hisi_clk_remove(pdev);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(hisi_crg_probe);
+
+int hisi_crg_remove(struct platform_device *pdev)
+{
+ struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
+
+ hisi_reset_exit(crg->rstc);
+ hisi_clk_remove(pdev);
+ return 0;
+}
+EXPORT_SYMBOL_GPL(hisi_crg_remove);
--
2.39.2
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v2 1/4] clk: hisilicon: Add helper functions for platform driver
2023-03-29 7:50 ` [PATCH v2 1/4] clk: hisilicon: Add helper functions for platform driver David Yang
@ 2023-04-05 19:51 ` Stephen Boyd
0 siblings, 0 replies; 9+ messages in thread
From: Stephen Boyd @ 2023-04-05 19:51 UTC (permalink / raw)
To: David Yang, linux-clk; +Cc: David Yang, Michael Turquette, linux-kernel
Quoting David Yang (2023-03-29 00:50:50)
> diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h
> index 7a9b42e1b027..def94498e14d 100644
> --- a/drivers/clk/hisilicon/clk.h
> +++ b/drivers/clk/hisilicon/clk.h
> @@ -103,6 +105,38 @@ struct hisi_gate_clock {
> const char *alias;
> };
>
> +struct hisi_clocks {
> + int nr;
> +
> + int (*prologue)(struct device *dev, struct hisi_clock_data *data);
> +
> + const struct hisi_fixed_rate_clock *fixed_rate_clks;
> + int fixed_rate_clks_num;
size_t for all these num types and 'nr'?
> +
> + const struct hisi_fixed_factor_clock *fixed_factor_clks;
> + int fixed_factor_clks_num;
> +
> + const struct hisi_mux_clock *mux_clks;
> + int mux_clks_num;
> +
> + const struct hisi_phase_clock *phase_clks;
> + int phase_clks_num;
> +
> + const struct hisi_divider_clock *divider_clks;
> + int divider_clks_num;
> +
> + const struct hisi_gate_clock *gate_clks;
> + int gate_clks_num;
> +
> + const struct hisi_gate_clock *gate_sep_clks;
> + int gate_sep_clks_num;
> +
> + const void *customized_clks;
> + int customized_clks_num;
> + int (*clk_register_customized)(struct device *dev, const void *clks,
> + int num, struct hisi_clock_data *data);
> +};
> +
> struct clk *hisi_register_clkgate_sep(struct device *, const char *,
> const char *, unsigned long,
> void __iomem *, u8,
> @@ -134,7 +169,16 @@ void hisi_clk_register_gate_sep(const struct hisi_gate_clock *,
> void hi6220_clk_register_divider(const struct hi6220_divider_clock *,
> int, struct hisi_clock_data *);
>
> -#define hisi_clk_unregister(type) \
> +int hisi_clk_register(struct device *dev, const struct hisi_clocks *clks,
> + struct hisi_clock_data *data);
> +
> +/* helper functions for platform driver */
> +
> +int hisi_clk_early_init(struct device_node *np, const struct hisi_clocks *clks);
> +int hisi_clk_probe(struct platform_device *pdev);
> +int hisi_clk_remove(struct platform_device *pdev);
> +
> +#define hisi_clk_unregister_fn(type) \
> static inline \
> void hisi_clk_unregister_##type(const struct hisi_##type##_clock *clks, \
> int nums, struct hisi_clock_data *data) \
> @@ -148,10 +192,10 @@ void hisi_clk_unregister_##type(const struct hisi_##type##_clock *clks, \
> } \
> }
>
> -hisi_clk_unregister(fixed_rate)
> -hisi_clk_unregister(fixed_factor)
> -hisi_clk_unregister(mux)
> -hisi_clk_unregister(divider)
> -hisi_clk_unregister(gate)
> +hisi_clk_unregister_fn(fixed_rate)
> +hisi_clk_unregister_fn(fixed_factor)
> +hisi_clk_unregister_fn(mux)
> +hisi_clk_unregister_fn(divider)
> +hisi_clk_unregister_fn(gate)
What does this hunk have to do with the $subject patch? Can you break
this series down into smaller patches? This is probably clearing the way
for hisi_clk_unregister() being an actual function, but I don't know. It
can
>
> #endif /* __HISI_CLK_H */
> diff --git a/drivers/clk/hisilicon/crg.h b/drivers/clk/hisilicon/crg.h
> index 803f6ba6d7a2..d9544f1f2625 100644
> --- a/drivers/clk/hisilicon/crg.h
> +++ b/drivers/clk/hisilicon/crg.h
> @@ -22,4 +22,9 @@ struct hisi_crg_dev {
> const struct hisi_crg_funcs *funcs;
> };
>
> +/* helper functions for platform driver */
> +
> +int hisi_crg_probe(struct platform_device *pdev);
> +int hisi_crg_remove(struct platform_device *pdev);
> +
> #endif /* __HISI_CRG_H */
> diff --git a/drivers/clk/hisilicon/reset.c b/drivers/clk/hisilicon/reset.c
> index 93cee17db8b1..3464e3b4d708 100644
> --- a/drivers/clk/hisilicon/reset.c
> +++ b/drivers/clk/hisilicon/reset.c
> @@ -5,12 +5,16 @@
> * Copyright (c) 2015-2016 HiSilicon Technologies Co., Ltd.
> */
>
> +#include <linux/device.h>
> #include <linux/io.h>
> +#include <linux/kernel.h>
> #include <linux/of_address.h>
> -#include <linux/platform_device.h>
Why?
> +#include <linux/of_device.h>
Why?
> #include <linux/reset-controller.h>
> -#include <linux/slab.h>
Why?
> #include <linux/spinlock.h>
> +
> +#include "clk.h"
> +#include "crg.h"
> #include "reset.h"
>
> #define HISI_RESET_BIT_MASK 0x1f
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 2/4] clk: hisilicon: Use helper functions
2023-03-29 7:50 [PATCH v2 0/4] clk: hisilicon: Migrate devm APIs David Yang
2023-03-29 7:50 ` [PATCH v2 1/4] clk: hisilicon: Add helper functions for platform driver David Yang
@ 2023-03-29 7:50 ` David Yang
2023-04-05 21:06 ` Stephen Boyd
2023-03-29 7:50 ` [PATCH v2 3/4] clk: hisilicon: Convert to platform driver David Yang
` (2 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: David Yang @ 2023-03-29 7:50 UTC (permalink / raw)
To: linux-clk
Cc: David Yang, Michael Turquette, Stephen Boyd, linux-kernel,
Conor Dooley, Nick Alcock
Remove redundant codes.
Signed-off-by: David Yang <mmyangfl@gmail.com>
---
drivers/clk/hisilicon/clk-hi3519.c | 134 ++----------
drivers/clk/hisilicon/clk-hi3559a.c | 228 +++-----------------
drivers/clk/hisilicon/clk-hi3660.c | 207 ++++++------------
drivers/clk/hisilicon/clk-hi3670.c | 270 +++++++++---------------
drivers/clk/hisilicon/crg-hi3516cv300.c | 177 ++--------------
drivers/clk/hisilicon/crg-hi3798cv200.c | 206 +++---------------
drivers/clk/hisilicon/crg.h | 6 -
7 files changed, 260 insertions(+), 968 deletions(-)
diff --git a/drivers/clk/hisilicon/clk-hi3519.c b/drivers/clk/hisilicon/clk-hi3519.c
index ad0c7f350cf0..199d1b8c3140 100644
--- a/drivers/clk/hisilicon/clk-hi3519.c
+++ b/drivers/clk/hisilicon/clk-hi3519.c
@@ -6,11 +6,13 @@
*/
#include <dt-bindings/clock/hi3519-clock.h>
-#include <linux/clk-provider.h>
+
+#include <linux/kernel.h>
#include <linux/module.h>
-#include <linux/platform_device.h>
+#include <linux/of_device.h>
+
#include "clk.h"
-#include "reset.h"
+#include "crg.h"
#define HI3519_INNER_CLK_OFFSET 64
#define HI3519_FIXED_24M 65
@@ -73,131 +75,33 @@ static const struct hisi_gate_clock hi3519_gate_clks[] = {
CLK_SET_RATE_PARENT, 0xe4, 18, 0, },
};
-static struct hisi_clock_data *hi3519_clk_register(struct platform_device *pdev)
-{
- struct hisi_clock_data *clk_data;
- int ret;
-
- clk_data = hisi_clk_alloc(pdev, HI3519_NR_CLKS);
- if (!clk_data)
- return ERR_PTR(-ENOMEM);
-
- ret = hisi_clk_register_fixed_rate(hi3519_fixed_rate_clks,
- ARRAY_SIZE(hi3519_fixed_rate_clks),
- clk_data);
- if (ret)
- return ERR_PTR(ret);
-
- ret = hisi_clk_register_mux(hi3519_mux_clks,
- ARRAY_SIZE(hi3519_mux_clks),
- clk_data);
- if (ret)
- goto unregister_fixed_rate;
-
- ret = hisi_clk_register_gate(hi3519_gate_clks,
- ARRAY_SIZE(hi3519_gate_clks),
- clk_data);
- if (ret)
- goto unregister_mux;
-
- ret = of_clk_add_provider(pdev->dev.of_node,
- of_clk_src_onecell_get, &clk_data->clk_data);
- if (ret)
- goto unregister_gate;
-
- return clk_data;
-
-unregister_fixed_rate:
- hisi_clk_unregister_fixed_rate(hi3519_fixed_rate_clks,
- ARRAY_SIZE(hi3519_fixed_rate_clks),
- clk_data);
-
-unregister_mux:
- hisi_clk_unregister_mux(hi3519_mux_clks,
- ARRAY_SIZE(hi3519_mux_clks),
- clk_data);
-unregister_gate:
- hisi_clk_unregister_gate(hi3519_gate_clks,
- ARRAY_SIZE(hi3519_gate_clks),
- clk_data);
- return ERR_PTR(ret);
-}
-
-static void hi3519_clk_unregister(struct platform_device *pdev)
-{
- struct hi3519_crg_data *crg = platform_get_drvdata(pdev);
-
- of_clk_del_provider(pdev->dev.of_node);
-
- hisi_clk_unregister_gate(hi3519_gate_clks,
- ARRAY_SIZE(hi3519_mux_clks),
- crg->clk_data);
- hisi_clk_unregister_mux(hi3519_mux_clks,
- ARRAY_SIZE(hi3519_mux_clks),
- crg->clk_data);
- hisi_clk_unregister_fixed_rate(hi3519_fixed_rate_clks,
- ARRAY_SIZE(hi3519_fixed_rate_clks),
- crg->clk_data);
-}
-
-static int hi3519_clk_probe(struct platform_device *pdev)
-{
- struct hi3519_crg_data *crg;
-
- crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
- if (!crg)
- return -ENOMEM;
-
- crg->rstc = hisi_reset_init(pdev);
- if (!crg->rstc)
- return -ENOMEM;
-
- crg->clk_data = hi3519_clk_register(pdev);
- if (IS_ERR(crg->clk_data)) {
- hisi_reset_exit(crg->rstc);
- return PTR_ERR(crg->clk_data);
- }
-
- platform_set_drvdata(pdev, crg);
- return 0;
-}
-
-static int hi3519_clk_remove(struct platform_device *pdev)
-{
- struct hi3519_crg_data *crg = platform_get_drvdata(pdev);
-
- hisi_reset_exit(crg->rstc);
- hi3519_clk_unregister(pdev);
- return 0;
-}
-
+static const struct hisi_clocks hi3519_crg_clks = {
+ .nr = HI3519_NR_CLKS,
+ .fixed_rate_clks = hi3519_fixed_rate_clks,
+ .fixed_rate_clks_num = ARRAY_SIZE(hi3519_fixed_rate_clks),
+ .mux_clks = hi3519_mux_clks,
+ .mux_clks_num = ARRAY_SIZE(hi3519_mux_clks),
+ .gate_clks = hi3519_gate_clks,
+ .gate_clks_num = ARRAY_SIZE(hi3519_gate_clks),
+};
static const struct of_device_id hi3519_clk_match_table[] = {
- { .compatible = "hisilicon,hi3519-crg" },
+ { .compatible = "hisilicon,hi3519-crg",
+ .data = &hi3519_crg_clks },
{ }
};
MODULE_DEVICE_TABLE(of, hi3519_clk_match_table);
static struct platform_driver hi3519_clk_driver = {
- .probe = hi3519_clk_probe,
- .remove = hi3519_clk_remove,
+ .probe = hisi_crg_probe,
+ .remove = hisi_crg_remove,
.driver = {
.name = "hi3519-clk",
.of_match_table = hi3519_clk_match_table,
},
};
-static int __init hi3519_clk_init(void)
-{
- return platform_driver_register(&hi3519_clk_driver);
-}
-core_initcall(hi3519_clk_init);
-
-static void __exit hi3519_clk_exit(void)
-{
- platform_driver_unregister(&hi3519_clk_driver);
-}
-module_exit(hi3519_clk_exit);
+module_platform_driver(hi3519_clk_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("HiSilicon Hi3519 Clock Driver");
diff --git a/drivers/clk/hisilicon/clk-hi3559a.c b/drivers/clk/hisilicon/clk-hi3559a.c
index 8036bd8cbb0a..d641b2a759dd 100644
--- a/drivers/clk/hisilicon/clk-hi3559a.c
+++ b/drivers/clk/hisilicon/clk-hi3559a.c
@@ -11,7 +11,6 @@
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
-#include <linux/slab.h>
#include <dt-bindings/clock/hi3559av100-clock.h>
@@ -452,9 +451,11 @@ static const struct clk_ops hisi_clk_pll_ops = {
.recalc_rate = clk_pll_recalc_rate,
};
-static void hisi_clk_register_pll(struct hi3559av100_pll_clock *clks,
- int nums, struct hisi_clock_data *data, struct device *dev)
+static int
+hisi_clk_register_pll(struct device *dev, const void *clocks,
+ int nums, struct hisi_clock_data *data)
{
+ const struct hi3559av100_pll_clock *clks = clocks;
void __iomem *base = data->base;
struct hi3559av100_clk_pll *p_clk = NULL;
struct clk *clk = NULL;
@@ -464,7 +465,7 @@ static void hisi_clk_register_pll(struct hi3559av100_pll_clock *clks,
p_clk = devm_kzalloc(dev, sizeof(*p_clk) * nums, GFP_KERNEL);
if (!p_clk)
- return;
+ return -ENOMEM;
for (i = 0; i < nums; i++) {
init.name = clks[i].name;
@@ -494,78 +495,27 @@ static void hisi_clk_register_pll(struct hi3559av100_pll_clock *clks,
devm_kfree(dev, p_clk);
dev_err(dev, "%s: failed to register clock %s\n",
__func__, clks[i].name);
- continue;
+ return PTR_ERR(clk);
}
data->clk_data.clks[clks[i].id] = clk;
p_clk++;
}
-}
-
-static struct hisi_clock_data *hi3559av100_clk_register(
- struct platform_device *pdev)
-{
- struct hisi_clock_data *clk_data;
- int ret;
-
- clk_data = hisi_clk_alloc(pdev, HI3559AV100_CRG_NR_CLKS);
- if (!clk_data)
- return ERR_PTR(-ENOMEM);
-
- ret = hisi_clk_register_fixed_rate(hi3559av100_fixed_rate_clks_crg,
- ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), clk_data);
- if (ret)
- return ERR_PTR(ret);
-
- hisi_clk_register_pll(hi3559av100_pll_clks,
- ARRAY_SIZE(hi3559av100_pll_clks), clk_data, &pdev->dev);
-
- ret = hisi_clk_register_mux(hi3559av100_mux_clks_crg,
- ARRAY_SIZE(hi3559av100_mux_clks_crg), clk_data);
- if (ret)
- goto unregister_fixed_rate;
-
- ret = hisi_clk_register_gate(hi3559av100_gate_clks,
- ARRAY_SIZE(hi3559av100_gate_clks), clk_data);
- if (ret)
- goto unregister_mux;
-
- ret = of_clk_add_provider(pdev->dev.of_node,
- of_clk_src_onecell_get, &clk_data->clk_data);
- if (ret)
- goto unregister_gate;
-
- return clk_data;
-
-unregister_gate:
- hisi_clk_unregister_gate(hi3559av100_gate_clks,
- ARRAY_SIZE(hi3559av100_gate_clks), clk_data);
-unregister_mux:
- hisi_clk_unregister_mux(hi3559av100_mux_clks_crg,
- ARRAY_SIZE(hi3559av100_mux_clks_crg), clk_data);
-unregister_fixed_rate:
- hisi_clk_unregister_fixed_rate(hi3559av100_fixed_rate_clks_crg,
- ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), clk_data);
- return ERR_PTR(ret);
-}
-static void hi3559av100_clk_unregister(struct platform_device *pdev)
-{
- struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
-
- of_clk_del_provider(pdev->dev.of_node);
-
- hisi_clk_unregister_gate(hi3559av100_gate_clks,
- ARRAY_SIZE(hi3559av100_gate_clks), crg->clk_data);
- hisi_clk_unregister_mux(hi3559av100_mux_clks_crg,
- ARRAY_SIZE(hi3559av100_mux_clks_crg), crg->clk_data);
- hisi_clk_unregister_fixed_rate(hi3559av100_fixed_rate_clks_crg,
- ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), crg->clk_data);
+ return 0;
}
-static const struct hisi_crg_funcs hi3559av100_crg_funcs = {
- .register_clks = hi3559av100_clk_register,
- .unregister_clks = hi3559av100_clk_unregister,
+static const struct hisi_clocks hi3559av100_clks = {
+ .nr = HI3559AV100_CRG_NR_CLKS,
+ .fixed_rate_clks = hi3559av100_fixed_rate_clks_crg,
+ .fixed_rate_clks_num = ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg),
+ .mux_clks = hi3559av100_mux_clks_crg,
+ .mux_clks_num = ARRAY_SIZE(hi3559av100_mux_clks_crg),
+ .gate_clks = hi3559av100_gate_clks,
+ .gate_clks_num = ARRAY_SIZE(hi3559av100_gate_clks),
+ .customized_clks = hi3559av100_pll_clks,
+ .customized_clks_num = ARRAY_SIZE(hi3559av100_pll_clks),
+ .clk_register_customized = hisi_clk_register_pll,
};
static struct hisi_fixed_rate_clock hi3559av100_shub_fixed_rate_clks[] = {
@@ -673,7 +623,7 @@ static struct hisi_gate_clock hi3559av100_shub_gate_clks[] = {
},
};
-static int hi3559av100_shub_default_clk_set(void)
+static int hi3559av100_shub_default_clk_set(struct device *dev, struct hisi_clock_data *data)
{
void __iomem *crg_base;
unsigned int val;
@@ -696,149 +646,41 @@ static int hi3559av100_shub_default_clk_set(void)
return 0;
}
-static struct hisi_clock_data *hi3559av100_shub_clk_register(
- struct platform_device *pdev)
-{
- struct hisi_clock_data *clk_data = NULL;
- int ret;
-
- hi3559av100_shub_default_clk_set();
-
- clk_data = hisi_clk_alloc(pdev, HI3559AV100_SHUB_NR_CLKS);
- if (!clk_data)
- return ERR_PTR(-ENOMEM);
-
- ret = hisi_clk_register_fixed_rate(hi3559av100_shub_fixed_rate_clks,
- ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), clk_data);
- if (ret)
- return ERR_PTR(ret);
-
- ret = hisi_clk_register_mux(hi3559av100_shub_mux_clks,
- ARRAY_SIZE(hi3559av100_shub_mux_clks), clk_data);
- if (ret)
- goto unregister_fixed_rate;
-
- ret = hisi_clk_register_divider(hi3559av100_shub_div_clks,
- ARRAY_SIZE(hi3559av100_shub_div_clks), clk_data);
- if (ret)
- goto unregister_mux;
-
- ret = hisi_clk_register_gate(hi3559av100_shub_gate_clks,
- ARRAY_SIZE(hi3559av100_shub_gate_clks), clk_data);
- if (ret)
- goto unregister_factor;
-
- ret = of_clk_add_provider(pdev->dev.of_node,
- of_clk_src_onecell_get, &clk_data->clk_data);
- if (ret)
- goto unregister_gate;
-
- return clk_data;
-
-unregister_gate:
- hisi_clk_unregister_gate(hi3559av100_shub_gate_clks,
- ARRAY_SIZE(hi3559av100_shub_gate_clks), clk_data);
-unregister_factor:
- hisi_clk_unregister_divider(hi3559av100_shub_div_clks,
- ARRAY_SIZE(hi3559av100_shub_div_clks), clk_data);
-unregister_mux:
- hisi_clk_unregister_mux(hi3559av100_shub_mux_clks,
- ARRAY_SIZE(hi3559av100_shub_mux_clks), clk_data);
-unregister_fixed_rate:
- hisi_clk_unregister_fixed_rate(hi3559av100_shub_fixed_rate_clks,
- ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), clk_data);
- return ERR_PTR(ret);
-}
-
-static void hi3559av100_shub_clk_unregister(struct platform_device *pdev)
-{
- struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
-
- of_clk_del_provider(pdev->dev.of_node);
-
- hisi_clk_unregister_gate(hi3559av100_shub_gate_clks,
- ARRAY_SIZE(hi3559av100_shub_gate_clks), crg->clk_data);
- hisi_clk_unregister_divider(hi3559av100_shub_div_clks,
- ARRAY_SIZE(hi3559av100_shub_div_clks), crg->clk_data);
- hisi_clk_unregister_mux(hi3559av100_shub_mux_clks,
- ARRAY_SIZE(hi3559av100_shub_mux_clks), crg->clk_data);
- hisi_clk_unregister_fixed_rate(hi3559av100_shub_fixed_rate_clks,
- ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), crg->clk_data);
-}
-
-static const struct hisi_crg_funcs hi3559av100_shub_crg_funcs = {
- .register_clks = hi3559av100_shub_clk_register,
- .unregister_clks = hi3559av100_shub_clk_unregister,
+static const struct hisi_clocks hi3559av100_shub_clks = {
+ .nr = HI3559AV100_SHUB_NR_CLKS,
+ .prologue = hi3559av100_shub_default_clk_set,
+ .fixed_rate_clks = hi3559av100_shub_fixed_rate_clks,
+ .fixed_rate_clks_num = ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks),
+ .mux_clks = hi3559av100_shub_mux_clks,
+ .mux_clks_num = ARRAY_SIZE(hi3559av100_shub_mux_clks),
+ .divider_clks = hi3559av100_shub_div_clks,
+ .divider_clks_num = ARRAY_SIZE(hi3559av100_shub_div_clks),
+ .gate_clks = hi3559av100_shub_gate_clks,
+ .gate_clks_num = ARRAY_SIZE(hi3559av100_shub_gate_clks),
};
static const struct of_device_id hi3559av100_crg_match_table[] = {
{
.compatible = "hisilicon,hi3559av100-clock",
- .data = &hi3559av100_crg_funcs
+ .data = &hi3559av100_clks
},
{
.compatible = "hisilicon,hi3559av100-shub-clock",
- .data = &hi3559av100_shub_crg_funcs
+ .data = &hi3559av100_shub_clks
},
{ }
};
MODULE_DEVICE_TABLE(of, hi3559av100_crg_match_table);
-static int hi3559av100_crg_probe(struct platform_device *pdev)
-{
- struct hisi_crg_dev *crg;
-
- crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
- if (!crg)
- return -ENOMEM;
-
- crg->funcs = of_device_get_match_data(&pdev->dev);
- if (!crg->funcs)
- return -ENOENT;
-
- crg->rstc = hisi_reset_init(pdev);
- if (!crg->rstc)
- return -ENOMEM;
-
- crg->clk_data = crg->funcs->register_clks(pdev);
- if (IS_ERR(crg->clk_data)) {
- hisi_reset_exit(crg->rstc);
- return PTR_ERR(crg->clk_data);
- }
-
- platform_set_drvdata(pdev, crg);
- return 0;
-}
-
-static int hi3559av100_crg_remove(struct platform_device *pdev)
-{
- struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
-
- hisi_reset_exit(crg->rstc);
- crg->funcs->unregister_clks(pdev);
- return 0;
-}
-
static struct platform_driver hi3559av100_crg_driver = {
- .probe = hi3559av100_crg_probe,
- .remove = hi3559av100_crg_remove,
+ .probe = hisi_crg_probe,
+ .remove = hisi_crg_remove,
.driver = {
.name = "hi3559av100-clock",
.of_match_table = hi3559av100_crg_match_table,
},
};
-static int __init hi3559av100_crg_init(void)
-{
- return platform_driver_register(&hi3559av100_crg_driver);
-}
-core_initcall(hi3559av100_crg_init);
-
-static void __exit hi3559av100_crg_exit(void)
-{
- platform_driver_unregister(&hi3559av100_crg_driver);
-}
-module_exit(hi3559av100_crg_exit);
-
+module_platform_driver(hi3559av100_crg_driver);
MODULE_DESCRIPTION("HiSilicon Hi3559AV100 CRG Driver");
diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c
index 41f61726ab19..c41b84545960 100644
--- a/drivers/clk/hisilicon/clk-hi3660.c
+++ b/drivers/clk/hisilicon/clk-hi3660.c
@@ -5,9 +5,11 @@
*/
#include <dt-bindings/clock/hi3660-clock.h>
-#include <linux/clk-provider.h>
+
+#include <linux/kernel.h>
+#include <linux/module.h>
#include <linux/of_device.h>
-#include <linux/platform_device.h>
+
#include "clk.h"
static const struct hisi_fixed_rate_clock hi3660_fixed_rate_clks[] = {
@@ -469,169 +471,92 @@ static const struct hisi_gate_clock hi3660_iomcu_gate_sep_clks[] = {
CLK_SET_RATE_PARENT, 0x90, 0, 0, },
};
-static struct hisi_clock_data *clk_crgctrl_data;
-
-static void hi3660_clk_iomcu_init(struct device_node *np)
-{
- struct hisi_clock_data *clk_data;
- int nr = ARRAY_SIZE(hi3660_iomcu_gate_sep_clks);
-
- clk_data = hisi_clk_init(np, nr);
- if (!clk_data)
- return;
-
- hisi_clk_register_gate_sep(hi3660_iomcu_gate_sep_clks,
- ARRAY_SIZE(hi3660_iomcu_gate_sep_clks),
- clk_data);
-}
-
-static void hi3660_clk_pmuctrl_init(struct device_node *np)
-{
- struct hisi_clock_data *clk_data;
- int nr = ARRAY_SIZE(hi3660_pmu_gate_clks);
-
- clk_data = hisi_clk_init(np, nr);
- if (!clk_data)
- return;
-
- hisi_clk_register_gate(hi3660_pmu_gate_clks,
- ARRAY_SIZE(hi3660_pmu_gate_clks), clk_data);
-}
+static const struct hisi_clocks hi3660_clk_iomcu_clks = {
+ .nr = ARRAY_SIZE(hi3660_iomcu_gate_sep_clks),
+ .gate_sep_clks = hi3660_iomcu_gate_sep_clks,
+ .gate_sep_clks_num = ARRAY_SIZE(hi3660_iomcu_gate_sep_clks),
+};
-static void hi3660_clk_pctrl_init(struct device_node *np)
-{
- struct hisi_clock_data *clk_data;
- int nr = ARRAY_SIZE(hi3660_pctrl_gate_clks);
+static const struct hisi_clocks hi3660_clk_pmuctrl_clks = {
+ .nr = ARRAY_SIZE(hi3660_pmu_gate_clks),
+ .gate_clks = hi3660_pmu_gate_clks,
+ .gate_clks_num = ARRAY_SIZE(hi3660_pmu_gate_clks),
+};
- clk_data = hisi_clk_init(np, nr);
- if (!clk_data)
- return;
- hisi_clk_register_gate(hi3660_pctrl_gate_clks,
- ARRAY_SIZE(hi3660_pctrl_gate_clks), clk_data);
-}
+static const struct hisi_clocks hi3660_clk_pctrl_clks = {
+ .nr = ARRAY_SIZE(hi3660_pctrl_gate_clks),
+ .gate_clks = hi3660_pctrl_gate_clks,
+ .gate_clks_num = ARRAY_SIZE(hi3660_pctrl_gate_clks),
+};
-static void hi3660_clk_sctrl_init(struct device_node *np)
-{
- struct hisi_clock_data *clk_data;
- int nr = ARRAY_SIZE(hi3660_sctrl_gate_clks) +
- ARRAY_SIZE(hi3660_sctrl_gate_sep_clks) +
- ARRAY_SIZE(hi3660_sctrl_mux_clks) +
- ARRAY_SIZE(hi3660_sctrl_divider_clks);
+static const struct hisi_clocks hi3660_clk_sctrl_clks = {
+ .nr = ARRAY_SIZE(hi3660_sctrl_mux_clks) +
+ ARRAY_SIZE(hi3660_sctrl_divider_clks) +
+ ARRAY_SIZE(hi3660_sctrl_gate_clks) +
+ ARRAY_SIZE(hi3660_sctrl_gate_sep_clks),
+ .mux_clks = hi3660_sctrl_mux_clks,
+ .mux_clks_num = ARRAY_SIZE(hi3660_sctrl_mux_clks),
+ .divider_clks = hi3660_sctrl_divider_clks,
+ .divider_clks_num = ARRAY_SIZE(hi3660_sctrl_divider_clks),
+ .gate_clks = hi3660_sctrl_gate_clks,
+ .gate_clks_num = ARRAY_SIZE(hi3660_sctrl_gate_clks),
+ .gate_sep_clks = hi3660_sctrl_gate_sep_clks,
+ .gate_sep_clks_num = ARRAY_SIZE(hi3660_sctrl_gate_sep_clks),
+};
- clk_data = hisi_clk_init(np, nr);
- if (!clk_data)
- return;
- hisi_clk_register_gate(hi3660_sctrl_gate_clks,
- ARRAY_SIZE(hi3660_sctrl_gate_clks), clk_data);
- hisi_clk_register_gate_sep(hi3660_sctrl_gate_sep_clks,
- ARRAY_SIZE(hi3660_sctrl_gate_sep_clks),
- clk_data);
- hisi_clk_register_mux(hi3660_sctrl_mux_clks,
- ARRAY_SIZE(hi3660_sctrl_mux_clks), clk_data);
- hisi_clk_register_divider(hi3660_sctrl_divider_clks,
- ARRAY_SIZE(hi3660_sctrl_divider_clks),
- clk_data);
-}
+static const struct hisi_clocks hi3660_clk_crgctrl_clks = {
+ .nr = ARRAY_SIZE(hi3660_fixed_rate_clks) +
+ ARRAY_SIZE(hi3660_crg_fixed_factor_clks) +
+ ARRAY_SIZE(hi3660_crgctrl_mux_clks) +
+ ARRAY_SIZE(hi3660_crgctrl_divider_clks) +
+ ARRAY_SIZE(hi3660_crgctrl_gate_clks) +
+ ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks),
+ .fixed_rate_clks = hi3660_fixed_rate_clks,
+ .fixed_rate_clks_num = ARRAY_SIZE(hi3660_fixed_rate_clks),
+ .fixed_factor_clks = hi3660_crg_fixed_factor_clks,
+ .fixed_factor_clks_num = ARRAY_SIZE(hi3660_crg_fixed_factor_clks),
+ .mux_clks = hi3660_crgctrl_mux_clks,
+ .mux_clks_num = ARRAY_SIZE(hi3660_crgctrl_mux_clks),
+ .divider_clks = hi3660_crgctrl_divider_clks,
+ .divider_clks_num = ARRAY_SIZE(hi3660_crgctrl_divider_clks),
+ .gate_clks = hi3660_crgctrl_gate_clks,
+ .gate_clks_num = ARRAY_SIZE(hi3660_crgctrl_gate_clks),
+ .gate_sep_clks = hi3660_crgctrl_gate_sep_clks,
+ .gate_sep_clks_num = ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks),
+};
static void hi3660_clk_crgctrl_early_init(struct device_node *np)
{
- int nr = ARRAY_SIZE(hi3660_fixed_rate_clks) +
- ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks) +
- ARRAY_SIZE(hi3660_crgctrl_gate_clks) +
- ARRAY_SIZE(hi3660_crgctrl_mux_clks) +
- ARRAY_SIZE(hi3660_crg_fixed_factor_clks) +
- ARRAY_SIZE(hi3660_crgctrl_divider_clks);
- int i;
-
- clk_crgctrl_data = hisi_clk_init(np, nr);
- if (!clk_crgctrl_data)
- return;
-
- for (i = 0; i < nr; i++)
- clk_crgctrl_data->clk_data.clks[i] = ERR_PTR(-EPROBE_DEFER);
-
- hisi_clk_register_fixed_rate(hi3660_fixed_rate_clks,
- ARRAY_SIZE(hi3660_fixed_rate_clks),
- clk_crgctrl_data);
+ hisi_clk_early_init(np, &hi3660_clk_crgctrl_clks);
}
CLK_OF_DECLARE_DRIVER(hi3660_clk_crgctrl, "hisilicon,hi3660-crgctrl",
hi3660_clk_crgctrl_early_init);
-static void hi3660_clk_crgctrl_init(struct device_node *np)
-{
- struct clk **clks;
- int i;
-
- if (!clk_crgctrl_data)
- hi3660_clk_crgctrl_early_init(np);
-
- /* clk_crgctrl_data initialization failed */
- if (!clk_crgctrl_data)
- return;
-
- hisi_clk_register_gate_sep(hi3660_crgctrl_gate_sep_clks,
- ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks),
- clk_crgctrl_data);
- hisi_clk_register_gate(hi3660_crgctrl_gate_clks,
- ARRAY_SIZE(hi3660_crgctrl_gate_clks),
- clk_crgctrl_data);
- hisi_clk_register_mux(hi3660_crgctrl_mux_clks,
- ARRAY_SIZE(hi3660_crgctrl_mux_clks),
- clk_crgctrl_data);
- hisi_clk_register_fixed_factor(hi3660_crg_fixed_factor_clks,
- ARRAY_SIZE(hi3660_crg_fixed_factor_clks),
- clk_crgctrl_data);
- hisi_clk_register_divider(hi3660_crgctrl_divider_clks,
- ARRAY_SIZE(hi3660_crgctrl_divider_clks),
- clk_crgctrl_data);
-
- clks = clk_crgctrl_data->clk_data.clks;
- for (i = 0; i < clk_crgctrl_data->clk_data.clk_num; i++) {
- if (IS_ERR(clks[i]) && PTR_ERR(clks[i]) != -EPROBE_DEFER)
- pr_err("Failed to register crgctrl clock[%d] err=%ld\n",
- i, PTR_ERR(clks[i]));
- }
-}
-
static const struct of_device_id hi3660_clk_match_table[] = {
{ .compatible = "hisilicon,hi3660-crgctrl",
- .data = hi3660_clk_crgctrl_init },
+ .data = &hi3660_clk_crgctrl_clks },
{ .compatible = "hisilicon,hi3660-pctrl",
- .data = hi3660_clk_pctrl_init },
+ .data = &hi3660_clk_pctrl_clks },
{ .compatible = "hisilicon,hi3660-pmuctrl",
- .data = hi3660_clk_pmuctrl_init },
+ .data = &hi3660_clk_pmuctrl_clks },
{ .compatible = "hisilicon,hi3660-sctrl",
- .data = hi3660_clk_sctrl_init },
+ .data = &hi3660_clk_sctrl_clks },
{ .compatible = "hisilicon,hi3660-iomcu",
- .data = hi3660_clk_iomcu_init },
+ .data = &hi3660_clk_iomcu_clks },
{ }
};
-
-static int hi3660_clk_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct device_node *np = pdev->dev.of_node;
- void (*init_func)(struct device_node *np);
-
- init_func = of_device_get_match_data(dev);
- if (!init_func)
- return -ENODEV;
-
- init_func(np);
-
- return 0;
-}
+MODULE_DEVICE_TABLE(of, hi3660_clk_match_table);
static struct platform_driver hi3660_clk_driver = {
- .probe = hi3660_clk_probe,
+ .probe = hisi_clk_probe,
+ .remove = hisi_clk_remove,
.driver = {
.name = "hi3660-clk",
.of_match_table = hi3660_clk_match_table,
},
};
-static int __init hi3660_clk_init(void)
-{
- return platform_driver_register(&hi3660_clk_driver);
-}
-core_initcall(hi3660_clk_init);
+module_platform_driver(hi3660_clk_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("HiSilicon Hi3660 Clock Driver");
diff --git a/drivers/clk/hisilicon/clk-hi3670.c b/drivers/clk/hisilicon/clk-hi3670.c
index 4d05a71683a5..8853a61ab808 100644
--- a/drivers/clk/hisilicon/clk-hi3670.c
+++ b/drivers/clk/hisilicon/clk-hi3670.c
@@ -8,9 +8,11 @@
*/
#include <dt-bindings/clock/hi3670-clock.h>
-#include <linux/clk-provider.h>
+
+#include <linux/kernel.h>
+#include <linux/module.h>
#include <linux/of_device.h>
-#include <linux/platform_device.h>
+
#include "clk.h"
static const struct hisi_fixed_rate_clock hi3670_fixed_rate_clks[] = {
@@ -822,195 +824,113 @@ static const struct hisi_gate_clock hi3670_media2_gate_sep_clks[] = {
CLK_SET_RATE_PARENT, 0x00, 2, 0, },
};
-static void hi3670_clk_crgctrl_init(struct device_node *np)
-{
- struct hisi_clock_data *clk_data;
-
- int nr = ARRAY_SIZE(hi3670_fixed_rate_clks) +
- ARRAY_SIZE(hi3670_crgctrl_gate_sep_clks) +
- ARRAY_SIZE(hi3670_crgctrl_gate_clks) +
- ARRAY_SIZE(hi3670_crgctrl_mux_clks) +
- ARRAY_SIZE(hi3670_crg_fixed_factor_clks) +
- ARRAY_SIZE(hi3670_crgctrl_divider_clks);
-
- clk_data = hisi_clk_init(np, nr);
- if (!clk_data)
- return;
-
- hisi_clk_register_fixed_rate(hi3670_fixed_rate_clks,
- ARRAY_SIZE(hi3670_fixed_rate_clks),
- clk_data);
- hisi_clk_register_gate_sep(hi3670_crgctrl_gate_sep_clks,
- ARRAY_SIZE(hi3670_crgctrl_gate_sep_clks),
- clk_data);
- hisi_clk_register_gate(hi3670_crgctrl_gate_clks,
- ARRAY_SIZE(hi3670_crgctrl_gate_clks),
- clk_data);
- hisi_clk_register_mux(hi3670_crgctrl_mux_clks,
- ARRAY_SIZE(hi3670_crgctrl_mux_clks),
- clk_data);
- hisi_clk_register_fixed_factor(hi3670_crg_fixed_factor_clks,
- ARRAY_SIZE(hi3670_crg_fixed_factor_clks),
- clk_data);
- hisi_clk_register_divider(hi3670_crgctrl_divider_clks,
- ARRAY_SIZE(hi3670_crgctrl_divider_clks),
- clk_data);
-}
-
-static void hi3670_clk_pctrl_init(struct device_node *np)
-{
- struct hisi_clock_data *clk_data;
- int nr = ARRAY_SIZE(hi3670_pctrl_gate_clks);
-
- clk_data = hisi_clk_init(np, nr);
- if (!clk_data)
- return;
- hisi_clk_register_gate(hi3670_pctrl_gate_clks,
- ARRAY_SIZE(hi3670_pctrl_gate_clks), clk_data);
-}
-
-static void hi3670_clk_pmuctrl_init(struct device_node *np)
-{
- struct hisi_clock_data *clk_data;
- int nr = ARRAY_SIZE(hi3670_pmu_gate_clks);
-
- clk_data = hisi_clk_init(np, nr);
- if (!clk_data)
- return;
-
- hisi_clk_register_gate(hi3670_pmu_gate_clks,
- ARRAY_SIZE(hi3670_pmu_gate_clks), clk_data);
-}
-
-static void hi3670_clk_sctrl_init(struct device_node *np)
-{
- struct hisi_clock_data *clk_data;
- int nr = ARRAY_SIZE(hi3670_sctrl_gate_sep_clks) +
- ARRAY_SIZE(hi3670_sctrl_gate_clks) +
- ARRAY_SIZE(hi3670_sctrl_mux_clks) +
- ARRAY_SIZE(hi3670_sctrl_divider_clks);
-
- clk_data = hisi_clk_init(np, nr);
- if (!clk_data)
- return;
-
- hisi_clk_register_gate_sep(hi3670_sctrl_gate_sep_clks,
- ARRAY_SIZE(hi3670_sctrl_gate_sep_clks),
- clk_data);
- hisi_clk_register_gate(hi3670_sctrl_gate_clks,
- ARRAY_SIZE(hi3670_sctrl_gate_clks),
- clk_data);
- hisi_clk_register_mux(hi3670_sctrl_mux_clks,
- ARRAY_SIZE(hi3670_sctrl_mux_clks),
- clk_data);
- hisi_clk_register_divider(hi3670_sctrl_divider_clks,
- ARRAY_SIZE(hi3670_sctrl_divider_clks),
- clk_data);
-}
-
-static void hi3670_clk_iomcu_init(struct device_node *np)
-{
- struct hisi_clock_data *clk_data;
- int nr = ARRAY_SIZE(hi3670_iomcu_gate_sep_clks) +
- ARRAY_SIZE(hi3670_iomcu_fixed_factor_clks);
-
- clk_data = hisi_clk_init(np, nr);
- if (!clk_data)
- return;
-
- hisi_clk_register_gate(hi3670_iomcu_gate_sep_clks,
- ARRAY_SIZE(hi3670_iomcu_gate_sep_clks), clk_data);
-
- hisi_clk_register_fixed_factor(hi3670_iomcu_fixed_factor_clks,
- ARRAY_SIZE(hi3670_iomcu_fixed_factor_clks),
- clk_data);
-}
-
-static void hi3670_clk_media1_init(struct device_node *np)
-{
- struct hisi_clock_data *clk_data;
-
- int nr = ARRAY_SIZE(hi3670_media1_gate_sep_clks) +
- ARRAY_SIZE(hi3670_media1_gate_clks) +
- ARRAY_SIZE(hi3670_media1_mux_clks) +
- ARRAY_SIZE(hi3670_media1_divider_clks);
-
- clk_data = hisi_clk_init(np, nr);
- if (!clk_data)
- return;
-
- hisi_clk_register_gate_sep(hi3670_media1_gate_sep_clks,
- ARRAY_SIZE(hi3670_media1_gate_sep_clks),
- clk_data);
- hisi_clk_register_gate(hi3670_media1_gate_clks,
- ARRAY_SIZE(hi3670_media1_gate_clks),
- clk_data);
- hisi_clk_register_mux(hi3670_media1_mux_clks,
- ARRAY_SIZE(hi3670_media1_mux_clks),
- clk_data);
- hisi_clk_register_divider(hi3670_media1_divider_clks,
- ARRAY_SIZE(hi3670_media1_divider_clks),
- clk_data);
-}
-
-static void hi3670_clk_media2_init(struct device_node *np)
-{
- struct hisi_clock_data *clk_data;
-
- int nr = ARRAY_SIZE(hi3670_media2_gate_sep_clks);
-
- clk_data = hisi_clk_init(np, nr);
- if (!clk_data)
- return;
-
- hisi_clk_register_gate_sep(hi3670_media2_gate_sep_clks,
- ARRAY_SIZE(hi3670_media2_gate_sep_clks),
- clk_data);
-}
+static const struct hisi_clocks hi3670_clk_crgctrl_clks = {
+ .nr = ARRAY_SIZE(hi3670_fixed_rate_clks) +
+ ARRAY_SIZE(hi3670_crg_fixed_factor_clks) +
+ ARRAY_SIZE(hi3670_crgctrl_mux_clks) +
+ ARRAY_SIZE(hi3670_crgctrl_divider_clks) +
+ ARRAY_SIZE(hi3670_crgctrl_gate_clks) +
+ ARRAY_SIZE(hi3670_crgctrl_gate_sep_clks),
+ .fixed_rate_clks = hi3670_fixed_rate_clks,
+ .fixed_rate_clks_num = ARRAY_SIZE(hi3670_fixed_rate_clks),
+ .fixed_factor_clks = hi3670_crg_fixed_factor_clks,
+ .fixed_factor_clks_num = ARRAY_SIZE(hi3670_crg_fixed_factor_clks),
+ .mux_clks = hi3670_crgctrl_mux_clks,
+ .mux_clks_num = ARRAY_SIZE(hi3670_crgctrl_mux_clks),
+ .divider_clks = hi3670_crgctrl_divider_clks,
+ .divider_clks_num = ARRAY_SIZE(hi3670_crgctrl_divider_clks),
+ .gate_clks = hi3670_crgctrl_gate_clks,
+ .gate_clks_num = ARRAY_SIZE(hi3670_crgctrl_gate_clks),
+ .gate_sep_clks = hi3670_crgctrl_gate_sep_clks,
+ .gate_sep_clks_num = ARRAY_SIZE(hi3670_crgctrl_gate_sep_clks),
+};
+
+static const struct hisi_clocks hi3670_clk_pctrl_clks = {
+ .nr = ARRAY_SIZE(hi3670_pctrl_gate_clks),
+ .gate_clks = hi3670_pctrl_gate_clks,
+ .gate_clks_num = ARRAY_SIZE(hi3670_pctrl_gate_clks),
+};
+
+static const struct hisi_clocks hi3670_clk_pmuctrl_clks = {
+ .nr = ARRAY_SIZE(hi3670_pmu_gate_clks),
+ .gate_clks = hi3670_pmu_gate_clks,
+ .gate_clks_num = ARRAY_SIZE(hi3670_pmu_gate_clks),
+};
+
+static const struct hisi_clocks hi3670_clk_sctrl_clks = {
+ .nr = ARRAY_SIZE(hi3670_sctrl_mux_clks) +
+ ARRAY_SIZE(hi3670_sctrl_divider_clks) +
+ ARRAY_SIZE(hi3670_sctrl_gate_clks) +
+ ARRAY_SIZE(hi3670_sctrl_gate_sep_clks),
+ .mux_clks = hi3670_sctrl_mux_clks,
+ .mux_clks_num = ARRAY_SIZE(hi3670_sctrl_mux_clks),
+ .divider_clks = hi3670_sctrl_divider_clks,
+ .divider_clks_num = ARRAY_SIZE(hi3670_sctrl_divider_clks),
+ .gate_clks = hi3670_sctrl_gate_clks,
+ .gate_clks_num = ARRAY_SIZE(hi3670_sctrl_gate_clks),
+ .gate_sep_clks = hi3670_sctrl_gate_sep_clks,
+ .gate_sep_clks_num = ARRAY_SIZE(hi3670_sctrl_gate_sep_clks),
+};
+
+static const struct hisi_clocks hi3670_clk_iomcu_clks = {
+ .nr = ARRAY_SIZE(hi3670_iomcu_fixed_factor_clks) +
+ ARRAY_SIZE(hi3670_iomcu_gate_sep_clks),
+ .fixed_factor_clks = hi3670_iomcu_fixed_factor_clks,
+ .fixed_factor_clks_num = ARRAY_SIZE(hi3670_iomcu_fixed_factor_clks),
+ .gate_clks = hi3670_iomcu_gate_sep_clks,
+ .gate_clks_num = ARRAY_SIZE(hi3670_iomcu_gate_sep_clks),
+};
+
+static const struct hisi_clocks hi3670_clk_media1_clks = {
+ .nr = ARRAY_SIZE(hi3670_media1_mux_clks) +
+ ARRAY_SIZE(hi3670_media1_divider_clks) +
+ ARRAY_SIZE(hi3670_media1_gate_clks) +
+ ARRAY_SIZE(hi3670_media1_gate_sep_clks),
+ .mux_clks = hi3670_media1_mux_clks,
+ .mux_clks_num = ARRAY_SIZE(hi3670_media1_mux_clks),
+ .divider_clks = hi3670_media1_divider_clks,
+ .divider_clks_num = ARRAY_SIZE(hi3670_media1_divider_clks),
+ .gate_clks = hi3670_media1_gate_clks,
+ .gate_clks_num = ARRAY_SIZE(hi3670_media1_gate_clks),
+ .gate_sep_clks = hi3670_media1_gate_sep_clks,
+ .gate_sep_clks_num = ARRAY_SIZE(hi3670_media1_gate_sep_clks),
+};
+
+static const struct hisi_clocks hi3670_clk_media2_clks = {
+ .nr = ARRAY_SIZE(hi3670_media2_gate_sep_clks),
+ .gate_sep_clks = hi3670_media2_gate_sep_clks,
+ .gate_sep_clks_num = ARRAY_SIZE(hi3670_media2_gate_sep_clks),
+};
static const struct of_device_id hi3670_clk_match_table[] = {
{ .compatible = "hisilicon,hi3670-crgctrl",
- .data = hi3670_clk_crgctrl_init },
+ .data = &hi3670_clk_crgctrl_clks },
{ .compatible = "hisilicon,hi3670-pctrl",
- .data = hi3670_clk_pctrl_init },
+ .data = &hi3670_clk_pctrl_clks },
{ .compatible = "hisilicon,hi3670-pmuctrl",
- .data = hi3670_clk_pmuctrl_init },
+ .data = &hi3670_clk_pmuctrl_clks },
{ .compatible = "hisilicon,hi3670-sctrl",
- .data = hi3670_clk_sctrl_init },
+ .data = &hi3670_clk_sctrl_clks },
{ .compatible = "hisilicon,hi3670-iomcu",
- .data = hi3670_clk_iomcu_init },
+ .data = &hi3670_clk_iomcu_clks },
{ .compatible = "hisilicon,hi3670-media1-crg",
- .data = hi3670_clk_media1_init },
+ .data = &hi3670_clk_media1_clks },
{ .compatible = "hisilicon,hi3670-media2-crg",
- .data = hi3670_clk_media2_init },
+ .data = &hi3670_clk_media2_clks },
{ }
};
-
-static int hi3670_clk_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct device_node *np = pdev->dev.of_node;
- void (*init_func)(struct device_node *np);
-
- init_func = of_device_get_match_data(dev);
- if (!init_func)
- return -ENODEV;
-
- init_func(np);
-
- return 0;
-}
+MODULE_DEVICE_TABLE(of, hi3670_clk_match_table);
static struct platform_driver hi3670_clk_driver = {
- .probe = hi3670_clk_probe,
+ .probe = hisi_clk_probe,
+ .remove = hisi_clk_remove,
.driver = {
.name = "hi3670-clk",
.of_match_table = hi3670_clk_match_table,
},
};
-static int __init hi3670_clk_init(void)
-{
- return platform_driver_register(&hi3670_clk_driver);
-}
-core_initcall(hi3670_clk_init);
+module_platform_driver(hi3670_clk_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("HiSilicon Hi3670 Clock Driver");
diff --git a/drivers/clk/hisilicon/crg-hi3516cv300.c b/drivers/clk/hisilicon/crg-hi3516cv300.c
index 5d4e61c7a429..0805852ecc87 100644
--- a/drivers/clk/hisilicon/crg-hi3516cv300.c
+++ b/drivers/clk/hisilicon/crg-hi3516cv300.c
@@ -6,13 +6,13 @@
*/
#include <dt-bindings/clock/hi3516cv300-clock.h>
-#include <linux/clk-provider.h>
+
+#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_device.h>
-#include <linux/platform_device.h>
+
#include "clk.h"
#include "crg.h"
-#include "reset.h"
/* hi3516CV300 core CRG */
#define HI3516CV300_INNER_CLK_OFFSET 64
@@ -126,67 +126,14 @@ static const struct hisi_gate_clock hi3516cv300_gate_clks[] = {
{ HI3516CV300_USB2_PHY_CLK, "clk_usb2_phy", NULL, 0, 0xb8, 7, 0, },
};
-static struct hisi_clock_data *hi3516cv300_clk_register(
- struct platform_device *pdev)
-{
- struct hisi_clock_data *clk_data;
- int ret;
-
- clk_data = hisi_clk_alloc(pdev, HI3516CV300_CRG_NR_CLKS);
- if (!clk_data)
- return ERR_PTR(-ENOMEM);
-
- ret = hisi_clk_register_fixed_rate(hi3516cv300_fixed_rate_clks,
- ARRAY_SIZE(hi3516cv300_fixed_rate_clks), clk_data);
- if (ret)
- return ERR_PTR(ret);
-
- ret = hisi_clk_register_mux(hi3516cv300_mux_clks,
- ARRAY_SIZE(hi3516cv300_mux_clks), clk_data);
- if (ret)
- goto unregister_fixed_rate;
-
- ret = hisi_clk_register_gate(hi3516cv300_gate_clks,
- ARRAY_SIZE(hi3516cv300_gate_clks), clk_data);
- if (ret)
- goto unregister_mux;
-
- ret = of_clk_add_provider(pdev->dev.of_node,
- of_clk_src_onecell_get, &clk_data->clk_data);
- if (ret)
- goto unregister_gate;
-
- return clk_data;
-
-unregister_gate:
- hisi_clk_unregister_gate(hi3516cv300_gate_clks,
- ARRAY_SIZE(hi3516cv300_gate_clks), clk_data);
-unregister_mux:
- hisi_clk_unregister_mux(hi3516cv300_mux_clks,
- ARRAY_SIZE(hi3516cv300_mux_clks), clk_data);
-unregister_fixed_rate:
- hisi_clk_unregister_fixed_rate(hi3516cv300_fixed_rate_clks,
- ARRAY_SIZE(hi3516cv300_fixed_rate_clks), clk_data);
- return ERR_PTR(ret);
-}
-
-static void hi3516cv300_clk_unregister(struct platform_device *pdev)
-{
- struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
-
- of_clk_del_provider(pdev->dev.of_node);
-
- hisi_clk_unregister_gate(hi3516cv300_gate_clks,
- ARRAY_SIZE(hi3516cv300_gate_clks), crg->clk_data);
- hisi_clk_unregister_mux(hi3516cv300_mux_clks,
- ARRAY_SIZE(hi3516cv300_mux_clks), crg->clk_data);
- hisi_clk_unregister_fixed_rate(hi3516cv300_fixed_rate_clks,
- ARRAY_SIZE(hi3516cv300_fixed_rate_clks), crg->clk_data);
-}
-
-static const struct hisi_crg_funcs hi3516cv300_crg_funcs = {
- .register_clks = hi3516cv300_clk_register,
- .unregister_clks = hi3516cv300_clk_unregister,
+static const struct hisi_clocks hi3516cv300_crg_clks = {
+ .nr = HI3516CV300_CRG_NR_CLKS,
+ .fixed_rate_clks = hi3516cv300_fixed_rate_clks,
+ .fixed_rate_clks_num = ARRAY_SIZE(hi3516cv300_fixed_rate_clks),
+ .mux_clks = hi3516cv300_mux_clks,
+ .mux_clks_num = ARRAY_SIZE(hi3516cv300_mux_clks),
+ .gate_clks = hi3516cv300_gate_clks,
+ .gate_clks_num = ARRAY_SIZE(hi3516cv300_gate_clks),
};
/* hi3516CV300 sysctrl CRG */
@@ -200,119 +147,35 @@ static const struct hisi_mux_clock hi3516cv300_sysctrl_mux_clks[] = {
CLK_SET_RATE_PARENT, 0x0, 23, 1, 0, wdt_mux_table, },
};
-static struct hisi_clock_data *hi3516cv300_sysctrl_clk_register(
- struct platform_device *pdev)
-{
- struct hisi_clock_data *clk_data;
- int ret;
-
- clk_data = hisi_clk_alloc(pdev, HI3516CV300_SYSCTRL_NR_CLKS);
- if (!clk_data)
- return ERR_PTR(-ENOMEM);
-
- ret = hisi_clk_register_mux(hi3516cv300_sysctrl_mux_clks,
- ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks), clk_data);
- if (ret)
- return ERR_PTR(ret);
-
-
- ret = of_clk_add_provider(pdev->dev.of_node,
- of_clk_src_onecell_get, &clk_data->clk_data);
- if (ret)
- goto unregister_mux;
-
- return clk_data;
-
-unregister_mux:
- hisi_clk_unregister_mux(hi3516cv300_sysctrl_mux_clks,
- ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks), clk_data);
- return ERR_PTR(ret);
-}
-
-static void hi3516cv300_sysctrl_clk_unregister(struct platform_device *pdev)
-{
- struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
-
- of_clk_del_provider(pdev->dev.of_node);
-
- hisi_clk_unregister_mux(hi3516cv300_sysctrl_mux_clks,
- ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks),
- crg->clk_data);
-}
-
-static const struct hisi_crg_funcs hi3516cv300_sysctrl_funcs = {
- .register_clks = hi3516cv300_sysctrl_clk_register,
- .unregister_clks = hi3516cv300_sysctrl_clk_unregister,
+static const struct hisi_clocks hi3516cv300_sysctrl_clks = {
+ .nr = HI3516CV300_SYSCTRL_NR_CLKS,
+ .mux_clks = hi3516cv300_sysctrl_mux_clks,
+ .mux_clks_num = ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks),
};
static const struct of_device_id hi3516cv300_crg_match_table[] = {
{
.compatible = "hisilicon,hi3516cv300-crg",
- .data = &hi3516cv300_crg_funcs
+ .data = &hi3516cv300_crg_clks,
},
{
.compatible = "hisilicon,hi3516cv300-sysctrl",
- .data = &hi3516cv300_sysctrl_funcs
+ .data = &hi3516cv300_sysctrl_clks,
},
{ }
};
MODULE_DEVICE_TABLE(of, hi3516cv300_crg_match_table);
-static int hi3516cv300_crg_probe(struct platform_device *pdev)
-{
- struct hisi_crg_dev *crg;
-
- crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
- if (!crg)
- return -ENOMEM;
-
- crg->funcs = of_device_get_match_data(&pdev->dev);
- if (!crg->funcs)
- return -ENOENT;
-
- crg->rstc = hisi_reset_init(pdev);
- if (!crg->rstc)
- return -ENOMEM;
-
- crg->clk_data = crg->funcs->register_clks(pdev);
- if (IS_ERR(crg->clk_data)) {
- hisi_reset_exit(crg->rstc);
- return PTR_ERR(crg->clk_data);
- }
-
- platform_set_drvdata(pdev, crg);
- return 0;
-}
-
-static int hi3516cv300_crg_remove(struct platform_device *pdev)
-{
- struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
-
- hisi_reset_exit(crg->rstc);
- crg->funcs->unregister_clks(pdev);
- return 0;
-}
-
static struct platform_driver hi3516cv300_crg_driver = {
- .probe = hi3516cv300_crg_probe,
- .remove = hi3516cv300_crg_remove,
+ .probe = hisi_crg_probe,
+ .remove = hisi_crg_remove,
.driver = {
.name = "hi3516cv300-crg",
.of_match_table = hi3516cv300_crg_match_table,
},
};
-static int __init hi3516cv300_crg_init(void)
-{
- return platform_driver_register(&hi3516cv300_crg_driver);
-}
-core_initcall(hi3516cv300_crg_init);
-
-static void __exit hi3516cv300_crg_exit(void)
-{
- platform_driver_unregister(&hi3516cv300_crg_driver);
-}
-module_exit(hi3516cv300_crg_exit);
+module_platform_driver(hi3516cv300_crg_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("HiSilicon Hi3516CV300 CRG Driver");
diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilicon/crg-hi3798cv200.c
index 08a19ba776e6..967e72099820 100644
--- a/drivers/clk/hisilicon/crg-hi3798cv200.c
+++ b/drivers/clk/hisilicon/crg-hi3798cv200.c
@@ -6,13 +6,13 @@
*/
#include <dt-bindings/clock/histb-clock.h>
-#include <linux/clk-provider.h>
+
+#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_device.h>
-#include <linux/platform_device.h>
+
#include "clk.h"
#include "crg.h"
-#include "reset.h"
/* hi3798CV200 core CRG */
#define HI3798CV200_INNER_CLK_OFFSET 64
@@ -41,6 +41,7 @@
#define HI3798CV200_CRG_NR_CLKS 128
+#define HI3798CV200_SYSCTRL_NR_CLKS 16
static const struct hisi_fixed_rate_clock hi3798cv200_fixed_rate_clks[] = {
{ HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, },
{ HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, },
@@ -193,90 +194,18 @@ static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {
CLK_SET_RATE_PARENT, 0xb0, 18, 0 },
};
-static struct hisi_clock_data *hi3798cv200_clk_register(
- struct platform_device *pdev)
-{
- struct hisi_clock_data *clk_data;
- int ret;
-
- clk_data = hisi_clk_alloc(pdev, HI3798CV200_CRG_NR_CLKS);
- if (!clk_data)
- return ERR_PTR(-ENOMEM);
-
- /* hisi_phase_clock is resource managed */
- ret = hisi_clk_register_phase(&pdev->dev,
- hi3798cv200_phase_clks,
- ARRAY_SIZE(hi3798cv200_phase_clks),
- clk_data);
- if (ret)
- return ERR_PTR(ret);
-
- ret = hisi_clk_register_fixed_rate(hi3798cv200_fixed_rate_clks,
- ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
- clk_data);
- if (ret)
- return ERR_PTR(ret);
-
- ret = hisi_clk_register_mux(hi3798cv200_mux_clks,
- ARRAY_SIZE(hi3798cv200_mux_clks),
- clk_data);
- if (ret)
- goto unregister_fixed_rate;
-
- ret = hisi_clk_register_gate(hi3798cv200_gate_clks,
- ARRAY_SIZE(hi3798cv200_gate_clks),
- clk_data);
- if (ret)
- goto unregister_mux;
-
- ret = of_clk_add_provider(pdev->dev.of_node,
- of_clk_src_onecell_get, &clk_data->clk_data);
- if (ret)
- goto unregister_gate;
-
- return clk_data;
-
-unregister_gate:
- hisi_clk_unregister_gate(hi3798cv200_gate_clks,
- ARRAY_SIZE(hi3798cv200_gate_clks),
- clk_data);
-unregister_mux:
- hisi_clk_unregister_mux(hi3798cv200_mux_clks,
- ARRAY_SIZE(hi3798cv200_mux_clks),
- clk_data);
-unregister_fixed_rate:
- hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks,
- ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
- clk_data);
- return ERR_PTR(ret);
-}
-
-static void hi3798cv200_clk_unregister(struct platform_device *pdev)
-{
- struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
-
- of_clk_del_provider(pdev->dev.of_node);
-
- hisi_clk_unregister_gate(hi3798cv200_gate_clks,
- ARRAY_SIZE(hi3798cv200_gate_clks),
- crg->clk_data);
- hisi_clk_unregister_mux(hi3798cv200_mux_clks,
- ARRAY_SIZE(hi3798cv200_mux_clks),
- crg->clk_data);
- hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks,
- ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
- crg->clk_data);
-}
-
-static const struct hisi_crg_funcs hi3798cv200_crg_funcs = {
- .register_clks = hi3798cv200_clk_register,
- .unregister_clks = hi3798cv200_clk_unregister,
+static const struct hisi_clocks hi3798cv200_crg_clks = {
+ .nr = HI3798CV200_CRG_NR_CLKS,
+ .fixed_rate_clks = hi3798cv200_fixed_rate_clks,
+ .fixed_rate_clks_num = ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
+ .mux_clks = hi3798cv200_mux_clks,
+ .mux_clks_num = ARRAY_SIZE(hi3798cv200_mux_clks),
+ .phase_clks = hi3798cv200_phase_clks,
+ .phase_clks_num = ARRAY_SIZE(hi3798cv200_phase_clks),
+ .gate_clks = hi3798cv200_gate_clks,
+ .gate_clks_num = ARRAY_SIZE(hi3798cv200_gate_clks),
};
-/* hi3798CV200 sysctrl CRG */
-
-#define HI3798CV200_SYSCTRL_NR_CLKS 16
-
static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = {
{ HISTB_IR_CLK, "clk_ir", "24m",
CLK_SET_RATE_PARENT, 0x48, 4, 0, },
@@ -286,116 +215,31 @@ static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = {
CLK_SET_RATE_PARENT, 0x48, 10, 0, },
};
-static struct hisi_clock_data *hi3798cv200_sysctrl_clk_register(
- struct platform_device *pdev)
-{
- struct hisi_clock_data *clk_data;
- int ret;
-
- clk_data = hisi_clk_alloc(pdev, HI3798CV200_SYSCTRL_NR_CLKS);
- if (!clk_data)
- return ERR_PTR(-ENOMEM);
-
- ret = hisi_clk_register_gate(hi3798cv200_sysctrl_gate_clks,
- ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
- clk_data);
- if (ret)
- return ERR_PTR(ret);
-
- ret = of_clk_add_provider(pdev->dev.of_node,
- of_clk_src_onecell_get, &clk_data->clk_data);
- if (ret)
- goto unregister_gate;
-
- return clk_data;
-
-unregister_gate:
- hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks,
- ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
- clk_data);
- return ERR_PTR(ret);
-}
-
-static void hi3798cv200_sysctrl_clk_unregister(struct platform_device *pdev)
-{
- struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
-
- of_clk_del_provider(pdev->dev.of_node);
-
- hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks,
- ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
- crg->clk_data);
-}
-
-static const struct hisi_crg_funcs hi3798cv200_sysctrl_funcs = {
- .register_clks = hi3798cv200_sysctrl_clk_register,
- .unregister_clks = hi3798cv200_sysctrl_clk_unregister,
+static const struct hisi_clocks hi3798cv200_sysctrl_clks = {
+ .nr = HI3798CV200_SYSCTRL_NR_CLKS,
+ .gate_clks = hi3798cv200_sysctrl_gate_clks,
+ .gate_clks_num = ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
};
static const struct of_device_id hi3798cv200_crg_match_table[] = {
{ .compatible = "hisilicon,hi3798cv200-crg",
- .data = &hi3798cv200_crg_funcs },
+ .data = &hi3798cv200_crg_clks },
{ .compatible = "hisilicon,hi3798cv200-sysctrl",
- .data = &hi3798cv200_sysctrl_funcs },
+ .data = &hi3798cv200_sysctrl_clks },
{ }
};
MODULE_DEVICE_TABLE(of, hi3798cv200_crg_match_table);
-static int hi3798cv200_crg_probe(struct platform_device *pdev)
-{
- struct hisi_crg_dev *crg;
-
- crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
- if (!crg)
- return -ENOMEM;
-
- crg->funcs = of_device_get_match_data(&pdev->dev);
- if (!crg->funcs)
- return -ENOENT;
-
- crg->rstc = hisi_reset_init(pdev);
- if (!crg->rstc)
- return -ENOMEM;
-
- crg->clk_data = crg->funcs->register_clks(pdev);
- if (IS_ERR(crg->clk_data)) {
- hisi_reset_exit(crg->rstc);
- return PTR_ERR(crg->clk_data);
- }
-
- platform_set_drvdata(pdev, crg);
- return 0;
-}
-
-static int hi3798cv200_crg_remove(struct platform_device *pdev)
-{
- struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
-
- hisi_reset_exit(crg->rstc);
- crg->funcs->unregister_clks(pdev);
- return 0;
-}
-
static struct platform_driver hi3798cv200_crg_driver = {
- .probe = hi3798cv200_crg_probe,
- .remove = hi3798cv200_crg_remove,
- .driver = {
- .name = "hi3798cv200-crg",
+ .probe = hisi_crg_probe,
+ .remove = hisi_crg_remove,
+ .driver = {
+ .name = "hi3798cv200-crg",
.of_match_table = hi3798cv200_crg_match_table,
},
};
-static int __init hi3798cv200_crg_init(void)
-{
- return platform_driver_register(&hi3798cv200_crg_driver);
-}
-core_initcall(hi3798cv200_crg_init);
-
-static void __exit hi3798cv200_crg_exit(void)
-{
- platform_driver_unregister(&hi3798cv200_crg_driver);
-}
-module_exit(hi3798cv200_crg_exit);
+module_platform_driver(hi3798cv200_crg_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("HiSilicon Hi3798CV200 CRG Driver");
diff --git a/drivers/clk/hisilicon/crg.h b/drivers/clk/hisilicon/crg.h
index d9544f1f2625..49142759d63b 100644
--- a/drivers/clk/hisilicon/crg.h
+++ b/drivers/clk/hisilicon/crg.h
@@ -11,15 +11,9 @@
struct hisi_clock_data;
struct hisi_reset_controller;
-struct hisi_crg_funcs {
- struct hisi_clock_data* (*register_clks)(struct platform_device *pdev);
- void (*unregister_clks)(struct platform_device *pdev);
-};
-
struct hisi_crg_dev {
struct hisi_clock_data *clk_data;
struct hisi_reset_controller *rstc;
- const struct hisi_crg_funcs *funcs;
};
/* helper functions for platform driver */
--
2.39.2
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v2 2/4] clk: hisilicon: Use helper functions
2023-03-29 7:50 ` [PATCH v2 2/4] clk: hisilicon: Use helper functions David Yang
@ 2023-04-05 21:06 ` Stephen Boyd
0 siblings, 0 replies; 9+ messages in thread
From: Stephen Boyd @ 2023-04-05 21:06 UTC (permalink / raw)
To: David Yang, linux-clk
Cc: David Yang, Michael Turquette, linux-kernel, Conor Dooley,
Nick Alcock
Quoting David Yang (2023-03-29 00:50:51)
> Remove redundant codes.
>
> Signed-off-by: David Yang <mmyangfl@gmail.com>
> ---
> drivers/clk/hisilicon/clk-hi3519.c | 134 ++----------
> drivers/clk/hisilicon/clk-hi3559a.c | 228 +++-----------------
> drivers/clk/hisilicon/clk-hi3660.c | 207 ++++++------------
> drivers/clk/hisilicon/clk-hi3670.c | 270 +++++++++---------------
> drivers/clk/hisilicon/crg-hi3516cv300.c | 177 ++--------------
> drivers/clk/hisilicon/crg-hi3798cv200.c | 206 +++---------------
Maybe you can do this file by file in a different patch? And the commit
text can say that you're migrating to the new way of registering clks
with a device pointer?
> drivers/clk/hisilicon/crg.h | 6 -
> 7 files changed, 260 insertions(+), 968 deletions(-)
>
> diff --git a/drivers/clk/hisilicon/clk-hi3519.c b/drivers/clk/hisilicon/clk-hi3519.c
> index ad0c7f350cf0..199d1b8c3140 100644
> --- a/drivers/clk/hisilicon/clk-hi3519.c
> +++ b/drivers/clk/hisilicon/clk-hi3519.c
> @@ -6,11 +6,13 @@
> */
>
> #include <dt-bindings/clock/hi3519-clock.h>
> -#include <linux/clk-provider.h>
It's still a clk provider. Keep this include.
> +
> +#include <linux/kernel.h>
> #include <linux/module.h>
> -#include <linux/platform_device.h>
Also still a platform driver. Keep this include.
> +#include <linux/of_device.h>
Not sure what this include is for.
> +
> #include "clk.h"
> -#include "reset.h"
> +#include "crg.h"
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 3/4] clk: hisilicon: Convert to platform driver
2023-03-29 7:50 [PATCH v2 0/4] clk: hisilicon: Migrate devm APIs David Yang
2023-03-29 7:50 ` [PATCH v2 1/4] clk: hisilicon: Add helper functions for platform driver David Yang
2023-03-29 7:50 ` [PATCH v2 2/4] clk: hisilicon: Use helper functions David Yang
@ 2023-03-29 7:50 ` David Yang
2023-04-05 21:08 ` Stephen Boyd
2023-03-29 7:50 ` [PATCH v2 4/4] clk: hisilicon: Migrate devm APIs David Yang
2023-04-05 19:39 ` [PATCH v2 0/4] " Stephen Boyd
4 siblings, 1 reply; 9+ messages in thread
From: David Yang @ 2023-03-29 7:50 UTC (permalink / raw)
To: linux-clk; +Cc: David Yang, Michael Turquette, Stephen Boyd, linux-kernel
And use common helper functions.
This patch is part of devm APIs migration.
Signed-off-by: David Yang <mmyangfl@gmail.com>
---
drivers/clk/hisilicon/clk-hi3620.c | 195 ++++++++++++------------
drivers/clk/hisilicon/clk-hi6220.c | 225 +++++++++++++---------------
drivers/clk/hisilicon/clk-hip04.c | 41 +++--
drivers/clk/hisilicon/clk-hix5hd2.c | 83 ++++++----
4 files changed, 281 insertions(+), 263 deletions(-)
diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk-hi3620.c
index a3d04c7c3da8..1eacf77b0d8c 100644
--- a/drivers/clk/hisilicon/clk-hi3620.c
+++ b/drivers/clk/hisilicon/clk-hi3620.c
@@ -12,6 +12,7 @@
#include <linux/kernel.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
+#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
@@ -22,48 +23,48 @@
#include "clk.h"
/* clock parent list */
-static const char *const timer0_mux_p[] __initconst = { "osc32k", "timerclk01", };
-static const char *const timer1_mux_p[] __initconst = { "osc32k", "timerclk01", };
-static const char *const timer2_mux_p[] __initconst = { "osc32k", "timerclk23", };
-static const char *const timer3_mux_p[] __initconst = { "osc32k", "timerclk23", };
-static const char *const timer4_mux_p[] __initconst = { "osc32k", "timerclk45", };
-static const char *const timer5_mux_p[] __initconst = { "osc32k", "timerclk45", };
-static const char *const timer6_mux_p[] __initconst = { "osc32k", "timerclk67", };
-static const char *const timer7_mux_p[] __initconst = { "osc32k", "timerclk67", };
-static const char *const timer8_mux_p[] __initconst = { "osc32k", "timerclk89", };
-static const char *const timer9_mux_p[] __initconst = { "osc32k", "timerclk89", };
-static const char *const uart0_mux_p[] __initconst = { "osc26m", "pclk", };
-static const char *const uart1_mux_p[] __initconst = { "osc26m", "pclk", };
-static const char *const uart2_mux_p[] __initconst = { "osc26m", "pclk", };
-static const char *const uart3_mux_p[] __initconst = { "osc26m", "pclk", };
-static const char *const uart4_mux_p[] __initconst = { "osc26m", "pclk", };
-static const char *const spi0_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };
-static const char *const spi1_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };
-static const char *const spi2_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };
+static const char *const timer0_mux_p[] = { "osc32k", "timerclk01", };
+static const char *const timer1_mux_p[] = { "osc32k", "timerclk01", };
+static const char *const timer2_mux_p[] = { "osc32k", "timerclk23", };
+static const char *const timer3_mux_p[] = { "osc32k", "timerclk23", };
+static const char *const timer4_mux_p[] = { "osc32k", "timerclk45", };
+static const char *const timer5_mux_p[] = { "osc32k", "timerclk45", };
+static const char *const timer6_mux_p[] = { "osc32k", "timerclk67", };
+static const char *const timer7_mux_p[] = { "osc32k", "timerclk67", };
+static const char *const timer8_mux_p[] = { "osc32k", "timerclk89", };
+static const char *const timer9_mux_p[] = { "osc32k", "timerclk89", };
+static const char *const uart0_mux_p[] = { "osc26m", "pclk", };
+static const char *const uart1_mux_p[] = { "osc26m", "pclk", };
+static const char *const uart2_mux_p[] = { "osc26m", "pclk", };
+static const char *const uart3_mux_p[] = { "osc26m", "pclk", };
+static const char *const uart4_mux_p[] = { "osc26m", "pclk", };
+static const char *const spi0_mux_p[] = { "osc26m", "rclk_cfgaxi", };
+static const char *const spi1_mux_p[] = { "osc26m", "rclk_cfgaxi", };
+static const char *const spi2_mux_p[] = { "osc26m", "rclk_cfgaxi", };
/* share axi parent */
-static const char *const saxi_mux_p[] __initconst = { "armpll3", "armpll2", };
-static const char *const pwm0_mux_p[] __initconst = { "osc32k", "osc26m", };
-static const char *const pwm1_mux_p[] __initconst = { "osc32k", "osc26m", };
-static const char *const sd_mux_p[] __initconst = { "armpll2", "armpll3", };
-static const char *const mmc1_mux_p[] __initconst = { "armpll2", "armpll3", };
-static const char *const mmc1_mux2_p[] __initconst = { "osc26m", "mmc1_div", };
-static const char *const g2d_mux_p[] __initconst = { "armpll2", "armpll3", };
-static const char *const venc_mux_p[] __initconst = { "armpll2", "armpll3", };
-static const char *const vdec_mux_p[] __initconst = { "armpll2", "armpll3", };
-static const char *const vpp_mux_p[] __initconst = { "armpll2", "armpll3", };
-static const char *const edc0_mux_p[] __initconst = { "armpll2", "armpll3", };
-static const char *const ldi0_mux_p[] __initconst = { "armpll2", "armpll4",
+static const char *const saxi_mux_p[] = { "armpll3", "armpll2", };
+static const char *const pwm0_mux_p[] = { "osc32k", "osc26m", };
+static const char *const pwm1_mux_p[] = { "osc32k", "osc26m", };
+static const char *const sd_mux_p[] = { "armpll2", "armpll3", };
+static const char *const mmc1_mux_p[] = { "armpll2", "armpll3", };
+static const char *const mmc1_mux2_p[] = { "osc26m", "mmc1_div", };
+static const char *const g2d_mux_p[] = { "armpll2", "armpll3", };
+static const char *const venc_mux_p[] = { "armpll2", "armpll3", };
+static const char *const vdec_mux_p[] = { "armpll2", "armpll3", };
+static const char *const vpp_mux_p[] = { "armpll2", "armpll3", };
+static const char *const edc0_mux_p[] = { "armpll2", "armpll3", };
+static const char *const ldi0_mux_p[] = { "armpll2", "armpll4",
"armpll3", "armpll5", };
-static const char *const edc1_mux_p[] __initconst = { "armpll2", "armpll3", };
-static const char *const ldi1_mux_p[] __initconst = { "armpll2", "armpll4",
+static const char *const edc1_mux_p[] = { "armpll2", "armpll3", };
+static const char *const ldi1_mux_p[] = { "armpll2", "armpll4",
"armpll3", "armpll5", };
-static const char *const rclk_hsic_p[] __initconst = { "armpll3", "armpll2", };
-static const char *const mmc2_mux_p[] __initconst = { "armpll2", "armpll3", };
-static const char *const mmc3_mux_p[] __initconst = { "armpll2", "armpll3", };
+static const char *const rclk_hsic_p[] = { "armpll3", "armpll2", };
+static const char *const mmc2_mux_p[] = { "armpll2", "armpll3", };
+static const char *const mmc3_mux_p[] = { "armpll2", "armpll3", };
/* fixed rate clocks */
-static struct hisi_fixed_rate_clock hi3620_fixed_rate_clks[] __initdata = {
+static struct hisi_fixed_rate_clock hi3620_fixed_rate_clks[] = {
{ HI3620_OSC32K, "osc32k", NULL, 0, 32768, },
{ HI3620_OSC26M, "osc26m", NULL, 0, 26000000, },
{ HI3620_PCLK, "pclk", NULL, 0, 26000000, },
@@ -76,13 +77,13 @@ static struct hisi_fixed_rate_clock hi3620_fixed_rate_clks[] __initdata = {
};
/* fixed factor clocks */
-static struct hisi_fixed_factor_clock hi3620_fixed_factor_clks[] __initdata = {
+static struct hisi_fixed_factor_clock hi3620_fixed_factor_clks[] = {
{ HI3620_RCLK_TCXO, "rclk_tcxo", "osc26m", 1, 4, 0, },
{ HI3620_RCLK_CFGAXI, "rclk_cfgaxi", "armpll2", 1, 30, 0, },
{ HI3620_RCLK_PICO, "rclk_pico", "hsic_div", 1, 40, 0, },
};
-static struct hisi_mux_clock hi3620_mux_clks[] __initdata = {
+static struct hisi_mux_clock hi3620_mux_clks[] = {
{ HI3620_TIMER0_MUX, "timer0_mux", timer0_mux_p, ARRAY_SIZE(timer0_mux_p), CLK_SET_RATE_PARENT, 0, 15, 2, 0, },
{ HI3620_TIMER1_MUX, "timer1_mux", timer1_mux_p, ARRAY_SIZE(timer1_mux_p), CLK_SET_RATE_PARENT, 0, 17, 2, 0, },
{ HI3620_TIMER2_MUX, "timer2_mux", timer2_mux_p, ARRAY_SIZE(timer2_mux_p), CLK_SET_RATE_PARENT, 0, 19, 2, 0, },
@@ -120,7 +121,7 @@ static struct hisi_mux_clock hi3620_mux_clks[] __initdata = {
{ HI3620_MMC3_MUX, "mmc3_mux", mmc3_mux_p, ARRAY_SIZE(mmc3_mux_p), CLK_SET_RATE_PARENT, 0x140, 9, 1, CLK_MUX_HIWORD_MASK, },
};
-static struct hisi_divider_clock hi3620_div_clks[] __initdata = {
+static struct hisi_divider_clock hi3620_div_clks[] = {
{ HI3620_SHAREAXI_DIV, "saxi_div", "saxi_mux", 0, 0x100, 0, 5, CLK_DIVIDER_HIWORD_MASK, NULL, },
{ HI3620_CFGAXI_DIV, "cfgaxi_div", "saxi_div", 0, 0x100, 5, 2, CLK_DIVIDER_HIWORD_MASK, NULL, },
{ HI3620_SD_DIV, "sd_div", "sd_mux", 0, 0x108, 0, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
@@ -130,7 +131,7 @@ static struct hisi_divider_clock hi3620_div_clks[] __initdata = {
{ HI3620_MMC3_DIV, "mmc3_div", "mmc3_mux", 0, 0x140, 5, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
};
-static struct hisi_gate_clock hi3620_separated_gate_clks[] __initdata = {
+static struct hisi_gate_clock hi3620_separated_gate_clks[] = {
{ HI3620_TIMERCLK01, "timerclk01", "timer_rclk01", CLK_SET_RATE_PARENT, 0x20, 0, 0, },
{ HI3620_TIMER_RCLK01, "timer_rclk01", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x20, 1, 0, },
{ HI3620_TIMERCLK23, "timerclk23", "timer_rclk23", CLK_SET_RATE_PARENT, 0x20, 2, 0, },
@@ -192,29 +193,19 @@ static struct hisi_gate_clock hi3620_separated_gate_clks[] __initdata = {
{ HI3620_MCU_CLK, "mcu_clk", "acp_clk", CLK_SET_RATE_PARENT, 0x50, 24, 0, },
};
-static void __init hi3620_clk_init(struct device_node *np)
-{
- struct hisi_clock_data *clk_data;
-
- clk_data = hisi_clk_init(np, HI3620_NR_CLKS);
- if (!clk_data)
- return;
-
- hisi_clk_register_fixed_rate(hi3620_fixed_rate_clks,
- ARRAY_SIZE(hi3620_fixed_rate_clks),
- clk_data);
- hisi_clk_register_fixed_factor(hi3620_fixed_factor_clks,
- ARRAY_SIZE(hi3620_fixed_factor_clks),
- clk_data);
- hisi_clk_register_mux(hi3620_mux_clks, ARRAY_SIZE(hi3620_mux_clks),
- clk_data);
- hisi_clk_register_divider(hi3620_div_clks, ARRAY_SIZE(hi3620_div_clks),
- clk_data);
- hisi_clk_register_gate_sep(hi3620_separated_gate_clks,
- ARRAY_SIZE(hi3620_separated_gate_clks),
- clk_data);
-}
-CLK_OF_DECLARE(hi3620_clk, "hisilicon,hi3620-clock", hi3620_clk_init);
+static const struct hisi_clocks hi3620_clks = {
+ .nr = HI3620_NR_CLKS,
+ .fixed_rate_clks = hi3620_fixed_rate_clks,
+ .fixed_rate_clks_num = ARRAY_SIZE(hi3620_fixed_rate_clks),
+ .fixed_factor_clks = hi3620_fixed_factor_clks,
+ .fixed_factor_clks_num = ARRAY_SIZE(hi3620_fixed_factor_clks),
+ .mux_clks = hi3620_mux_clks,
+ .mux_clks_num = ARRAY_SIZE(hi3620_mux_clks),
+ .divider_clks = hi3620_div_clks,
+ .divider_clks_num = ARRAY_SIZE(hi3620_div_clks),
+ .gate_sep_clks = hi3620_separated_gate_clks,
+ .gate_sep_clks_num = ARRAY_SIZE(hi3620_separated_gate_clks),
+};
struct hisi_mmc_clock {
unsigned int id;
@@ -252,7 +243,7 @@ struct clk_mmc {
#define to_mmc(_hw) container_of(_hw, struct clk_mmc, hw)
-static struct hisi_mmc_clock hi3620_mmc_clks[] __initdata = {
+static struct hisi_mmc_clock hi3620_mmc_clks[] = {
{ HI3620_SD_CIUCLK, "sd_bclk1", "sd_clk", CLK_SET_RATE_PARENT, 0x1f8, 0, 0x1f8, 1, 3, 0x1f8, 4, 4, 0x1f8, 8, 4},
{ HI3620_MMC_CIUCLK1, "mmc_bclk1", "mmc_clk1", CLK_SET_RATE_PARENT, 0x1f8, 12, 0x1f8, 13, 3, 0x1f8, 16, 4, 0x1f8, 20, 4},
{ HI3620_MMC_CIUCLK2, "mmc_bclk2", "mmc_clk2", CLK_SET_RATE_PARENT, 0x1f8, 24, 0x1f8, 25, 3, 0x1f8, 28, 4, 0x1fc, 0, 4},
@@ -408,8 +399,9 @@ static const struct clk_ops clk_mmc_ops = {
.recalc_rate = mmc_clk_recalc_rate,
};
-static struct clk *hisi_register_clk_mmc(struct hisi_mmc_clock *mmc_clk,
- void __iomem *base, struct device_node *np)
+static struct clk *
+clk_register_hisi_mmc(struct device *dev, const struct hisi_mmc_clock *mmc_clk,
+ void __iomem *base)
{
struct clk_mmc *mclk;
struct clk *clk;
@@ -445,39 +437,52 @@ static struct clk *hisi_register_clk_mmc(struct hisi_mmc_clock *mmc_clk,
return clk;
}
-static void __init hi3620_mmc_clk_init(struct device_node *node)
+static int hisi_register_clk_mmc(struct device *dev, const void *clocks,
+ int nums, struct hisi_clock_data *data)
{
- void __iomem *base;
- int i, num = ARRAY_SIZE(hi3620_mmc_clks);
- struct clk_onecell_data *clk_data;
-
- if (!node) {
- pr_err("failed to find pctrl node in DTS\n");
- return;
- }
-
- base = of_iomap(node, 0);
- if (!base) {
- pr_err("failed to map pctrl\n");
- return;
+ const struct hisi_mmc_clock *clks = clocks;
+ struct clk *clk;
+ int i;
+
+ for (i = 0; i < nums; i++) {
+ clk = clk_register_hisi_mmc(dev, &clks[i], data->base);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n",
+ __func__, clks[i].name);
+ return PTR_ERR(clk);
+ }
+ data->clk_data.clks[clks[i].id] = clk;
}
- clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
- if (WARN_ON(!clk_data))
- return;
+ return 0;
+}
- clk_data->clks = kcalloc(num, sizeof(*clk_data->clks), GFP_KERNEL);
- if (!clk_data->clks)
- return;
+static const struct hisi_clocks hi3620_clks_mmc = {
+ .nr = ARRAY_SIZE(hi3620_mmc_clks),
+ .customized_clks = hi3620_mmc_clks,
+ .customized_clks_num = ARRAY_SIZE(hi3620_mmc_clks),
+ .clk_register_customized = hisi_register_clk_mmc,
+};
- for (i = 0; i < num; i++) {
- struct hisi_mmc_clock *mmc_clk = &hi3620_mmc_clks[i];
- clk_data->clks[mmc_clk->id] =
- hisi_register_clk_mmc(mmc_clk, base, node);
- }
+static const struct of_device_id hi3620_clk_match_table[] = {
+ { .compatible = "hisilicon,hi3620-clock",
+ .data = &hi3620_clks },
+ { .compatible = "hisilicon,hi3620-mmc-clock",
+ .data = &hi3620_clks_mmc },
+ { }
+};
+MODULE_DEVICE_TABLE(of, hi3620_clk_match_table);
+
+static struct platform_driver hi3620_clk_driver = {
+ .probe = hisi_clk_probe,
+ .remove = hisi_clk_remove,
+ .driver = {
+ .name = "hi3620-clock",
+ .of_match_table = hi3620_clk_match_table,
+ },
+};
- clk_data->clk_num = num;
- of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-}
+module_platform_driver(hi3620_clk_driver);
-CLK_OF_DECLARE(hi3620_mmc_clk, "hisilicon,hi3620-mmc-clock", hi3620_mmc_clk_init);
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("HiSilicon Hi3620 Clock Driver");
diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c
index e7cdf72d4b06..cdc17f82ce2d 100644
--- a/drivers/clk/hisilicon/clk-hi6220.c
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -9,20 +9,15 @@
#include <linux/kernel.h>
#include <linux/clk-provider.h>
-#include <linux/clkdev.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
+#include <linux/module.h>
#include <linux/of_device.h>
-#include <linux/slab.h>
#include <dt-bindings/clock/hi6220-clock.h>
#include "clk.h"
-
/* clocks in AO (always on) controller */
-static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
+static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] = {
{ HI6220_REF32K, "ref32k", NULL, 0, 32764, },
{ HI6220_CLK_TCXO, "clk_tcxo", NULL, 0, 19200000, },
{ HI6220_MMC1_PAD, "mmc1_pad", NULL, 0, 100000000, },
@@ -38,7 +33,7 @@ static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
{ HI6220_PLL_DDR, "ddrpll0", NULL, 0, 1600000000,},
};
-static struct hisi_fixed_factor_clock hi6220_fixed_factor_clks[] __initdata = {
+static struct hisi_fixed_factor_clock hi6220_fixed_factor_clks[] = {
{ HI6220_300M, "clk_300m", "syspll", 1, 4, 0, },
{ HI6220_150M, "clk_150m", "clk_300m", 1, 2, 0, },
{ HI6220_PICOPHY_SRC, "picophy_src", "clk_150m", 1, 4, 0, },
@@ -51,7 +46,7 @@ static struct hisi_fixed_factor_clock hi6220_fixed_factor_clks[] __initdata = {
{ HI6220_MMC2_SMP, "mmc2_sample", "mmc2_sel", 1, 8, 0, },
};
-static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] __initdata = {
+static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] = {
{ HI6220_WDT0_PCLK, "wdt0_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 12, 0, },
{ HI6220_WDT1_PCLK, "wdt1_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 13, 0, },
{ HI6220_WDT2_PCLK, "wdt2_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 14, 0, },
@@ -69,47 +64,43 @@ static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] __initdata = {
{ HI6220_RTC1_PCLK, "rtc1_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 26, 0, },
};
-static void __init hi6220_clk_ao_init(struct device_node *np)
-{
- struct hisi_clock_data *clk_data_ao;
-
- clk_data_ao = hisi_clk_init(np, HI6220_AO_NR_CLKS);
- if (!clk_data_ao)
- return;
-
- hisi_clk_register_fixed_rate(hi6220_fixed_rate_clks,
- ARRAY_SIZE(hi6220_fixed_rate_clks), clk_data_ao);
-
- hisi_clk_register_fixed_factor(hi6220_fixed_factor_clks,
- ARRAY_SIZE(hi6220_fixed_factor_clks), clk_data_ao);
+static const struct hisi_clocks hi6220_ao_clks = {
+ .nr = HI6220_AO_NR_CLKS,
+ .fixed_rate_clks = hi6220_fixed_rate_clks,
+ .fixed_rate_clks_num = ARRAY_SIZE(hi6220_fixed_rate_clks),
+ .fixed_factor_clks = hi6220_fixed_factor_clks,
+ .fixed_factor_clks_num = ARRAY_SIZE(hi6220_fixed_factor_clks),
+ .gate_sep_clks = hi6220_separated_gate_clks_ao,
+ .gate_sep_clks_num = ARRAY_SIZE(hi6220_separated_gate_clks_ao),
+};
- hisi_clk_register_gate_sep(hi6220_separated_gate_clks_ao,
- ARRAY_SIZE(hi6220_separated_gate_clks_ao), clk_data_ao);
+static void hi6220_clk_ao_early_init(struct device_node *np)
+{
+ hisi_clk_early_init(np, &hi6220_ao_clks);
}
/* Allow reset driver to probe as well */
-CLK_OF_DECLARE_DRIVER(hi6220_clk_ao, "hisilicon,hi6220-aoctrl", hi6220_clk_ao_init);
-
+CLK_OF_DECLARE_DRIVER(hi6220_clk_ao, "hisilicon,hi6220-aoctrl", hi6220_clk_ao_early_init);
/* clocks in sysctrl */
-static const char *mmc0_mux0_p[] __initdata = { "pll_ddr_gate", "syspll", };
-static const char *mmc0_mux1_p[] __initdata = { "mmc0_mux0", "pll_media_gate", };
-static const char *mmc0_src_p[] __initdata = { "mmc0srcsel", "mmc0_div", };
-static const char *mmc1_mux0_p[] __initdata = { "pll_ddr_gate", "syspll", };
-static const char *mmc1_mux1_p[] __initdata = { "mmc1_mux0", "pll_media_gate", };
-static const char *mmc1_src_p[] __initdata = { "mmc1srcsel", "mmc1_div", };
-static const char *mmc2_mux0_p[] __initdata = { "pll_ddr_gate", "syspll", };
-static const char *mmc2_mux1_p[] __initdata = { "mmc2_mux0", "pll_media_gate", };
-static const char *mmc2_src_p[] __initdata = { "mmc2srcsel", "mmc2_div", };
-static const char *mmc0_sample_in[] __initdata = { "mmc0_sample", "mmc0_pad", };
-static const char *mmc1_sample_in[] __initdata = { "mmc1_sample", "mmc1_pad", };
-static const char *mmc2_sample_in[] __initdata = { "mmc2_sample", "mmc2_pad", };
-static const char *uart1_src[] __initdata = { "clk_tcxo", "clk_150m", };
-static const char *uart2_src[] __initdata = { "clk_tcxo", "clk_150m", };
-static const char *uart3_src[] __initdata = { "clk_tcxo", "clk_150m", };
-static const char *uart4_src[] __initdata = { "clk_tcxo", "clk_150m", };
-static const char *hifi_src[] __initdata = { "syspll", "pll_media_gate", };
-
-static struct hisi_gate_clock hi6220_separated_gate_clks_sys[] __initdata = {
+static const char * const mmc0_mux0_p[] = { "pll_ddr_gate", "syspll", };
+static const char * const mmc0_mux1_p[] = { "mmc0_mux0", "pll_media_gate", };
+static const char * const mmc0_src_p[] = { "mmc0srcsel", "mmc0_div", };
+static const char * const mmc1_mux0_p[] = { "pll_ddr_gate", "syspll", };
+static const char * const mmc1_mux1_p[] = { "mmc1_mux0", "pll_media_gate", };
+static const char * const mmc1_src_p[] = { "mmc1srcsel", "mmc1_div", };
+static const char * const mmc2_mux0_p[] = { "pll_ddr_gate", "syspll", };
+static const char * const mmc2_mux1_p[] = { "mmc2_mux0", "pll_media_gate", };
+static const char * const mmc2_src_p[] = { "mmc2srcsel", "mmc2_div", };
+static const char * const mmc0_sample_in[] = { "mmc0_sample", "mmc0_pad", };
+static const char * const mmc1_sample_in[] = { "mmc1_sample", "mmc1_pad", };
+static const char * const mmc2_sample_in[] = { "mmc2_sample", "mmc2_pad", };
+static const char * const uart1_src[] = { "clk_tcxo", "clk_150m", };
+static const char * const uart2_src[] = { "clk_tcxo", "clk_150m", };
+static const char * const uart3_src[] = { "clk_tcxo", "clk_150m", };
+static const char * const uart4_src[] = { "clk_tcxo", "clk_150m", };
+static const char * const hifi_src[] = { "syspll", "pll_media_gate", };
+
+static struct hisi_gate_clock hi6220_separated_gate_clks_sys[] = {
{ HI6220_MMC0_CLK, "mmc0_clk", "mmc0_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 0, 0, },
{ HI6220_MMC0_CIUCLK, "mmc0_ciuclk", "mmc0_smp_in", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 0, 0, },
{ HI6220_MMC1_CLK, "mmc1_clk", "mmc1_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 1, 0, },
@@ -146,7 +137,7 @@ static struct hisi_gate_clock hi6220_separated_gate_clks_sys[] __initdata = {
{ HI6220_CS_ATB_SYSPLL, "cs_atb_syspll", "syspll", CLK_SET_RATE_PARENT|CLK_IS_CRITICAL, 0x270, 12, 0, },
};
-static struct hisi_mux_clock hi6220_mux_clks_sys[] __initdata = {
+static struct hisi_mux_clock hi6220_mux_clks_sys[] = {
{ HI6220_MMC0_SRC, "mmc0_src", mmc0_src_p, ARRAY_SIZE(mmc0_src_p), CLK_SET_RATE_PARENT, 0x4, 0, 1, 0, },
{ HI6220_MMC0_SMP_IN, "mmc0_smp_in", mmc0_sample_in, ARRAY_SIZE(mmc0_sample_in), CLK_SET_RATE_PARENT, 0x4, 0, 1, 0, },
{ HI6220_MMC1_SRC, "mmc1_src", mmc1_src_p, ARRAY_SIZE(mmc1_src_p), CLK_SET_RATE_PARENT, 0x4, 2, 1, 0, },
@@ -166,7 +157,7 @@ static struct hisi_mux_clock hi6220_mux_clks_sys[] __initdata = {
{ HI6220_MMC2_MUX1, "mmc2_mux1", mmc2_mux1_p, ARRAY_SIZE(mmc2_mux1_p), CLK_SET_RATE_PARENT, 0x400, 15, 1, CLK_MUX_HIWORD_MASK,},
};
-static struct hi6220_divider_clock hi6220_div_clks_sys[] __initdata = {
+static struct hi6220_divider_clock hi6220_div_clks_sys[] = {
{ HI6220_CLK_BUS, "clk_bus", "clk_300m", CLK_SET_RATE_PARENT, 0x490, 0, 4, 7, },
{ HI6220_MMC0_DIV, "mmc0_div", "mmc0_syspll", CLK_SET_RATE_PARENT, 0x494, 0, 6, 7, },
{ HI6220_MMC1_DIV, "mmc1_div", "mmc1_syspll", CLK_SET_RATE_PARENT, 0x498, 0, 6, 7, },
@@ -177,32 +168,23 @@ static struct hi6220_divider_clock hi6220_div_clks_sys[] __initdata = {
{ HI6220_CS_ATB_DIV, "cs_atb_div", "cs_atb_syspll", CLK_SET_RATE_PARENT, 0x4a4, 0, 4, 7, },
};
-static void __init hi6220_clk_sys_init(struct device_node *np)
-{
- struct hisi_clock_data *clk_data;
-
- clk_data = hisi_clk_init(np, HI6220_SYS_NR_CLKS);
- if (!clk_data)
- return;
-
- hisi_clk_register_gate_sep(hi6220_separated_gate_clks_sys,
- ARRAY_SIZE(hi6220_separated_gate_clks_sys), clk_data);
-
- hisi_clk_register_mux(hi6220_mux_clks_sys,
- ARRAY_SIZE(hi6220_mux_clks_sys), clk_data);
-
- hi6220_clk_register_divider(hi6220_div_clks_sys,
- ARRAY_SIZE(hi6220_div_clks_sys), clk_data);
-}
-CLK_OF_DECLARE_DRIVER(hi6220_clk_sys, "hisilicon,hi6220-sysctrl", hi6220_clk_sys_init);
-
+static const struct hisi_clocks hi6220_sys_clks = {
+ .nr = HI6220_SYS_NR_CLKS,
+ .mux_clks = hi6220_mux_clks_sys,
+ .mux_clks_num = ARRAY_SIZE(hi6220_mux_clks_sys),
+ .gate_sep_clks = hi6220_separated_gate_clks_sys,
+ .gate_sep_clks_num = ARRAY_SIZE(hi6220_separated_gate_clks_sys),
+ .customized_clks = hi6220_div_clks_sys,
+ .customized_clks_num = ARRAY_SIZE(hi6220_div_clks_sys),
+ /* .clk_register_customized = hi6220_clk_register_divider, */
+};
/* clocks in media controller */
-static const char *clk_1000_1200_src[] __initdata = { "pll_gpu_gate", "media_syspll_src", };
-static const char *clk_1440_1200_src[] __initdata = { "media_syspll_src", "media_pll_src", };
-static const char *clk_1000_1440_src[] __initdata = { "pll_gpu_gate", "media_pll_src", };
+static const char * const clk_1000_1200_src[] = { "pll_gpu_gate", "media_syspll_src", };
+static const char * const clk_1440_1200_src[] = { "media_syspll_src", "media_pll_src", };
+static const char * const clk_1000_1440_src[] = { "pll_gpu_gate", "media_pll_src", };
-static struct hisi_gate_clock hi6220_separated_gate_clks_media[] __initdata = {
+static struct hisi_gate_clock hi6220_separated_gate_clks_media[] = {
{ HI6220_DSI_PCLK, "dsi_pclk", "vpucodec", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 0, 0, },
{ HI6220_G3D_PCLK, "g3d_pclk", "vpucodec", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 1, 0, },
{ HI6220_ACLK_CODEC_VPU, "aclk_codec_vpu", "ade_core_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 3, 0, },
@@ -218,13 +200,13 @@ static struct hisi_gate_clock hi6220_separated_gate_clks_media[] __initdata = {
{ HI6220_MED_SYSPLL, "media_syspll_src", "media_syspll", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 17, 0, },
};
-static struct hisi_mux_clock hi6220_mux_clks_media[] __initdata = {
+static struct hisi_mux_clock hi6220_mux_clks_media[] = {
{ HI6220_1440_1200, "clk_1440_1200", clk_1440_1200_src, ARRAY_SIZE(clk_1440_1200_src), CLK_SET_RATE_PARENT, 0x51c, 0, 1, 0, },
{ HI6220_1000_1200, "clk_1000_1200", clk_1000_1200_src, ARRAY_SIZE(clk_1000_1200_src), CLK_SET_RATE_PARENT, 0x51c, 1, 1, 0, },
{ HI6220_1000_1440, "clk_1000_1440", clk_1000_1440_src, ARRAY_SIZE(clk_1000_1440_src), CLK_SET_RATE_PARENT, 0x51c, 6, 1, 0, },
};
-static struct hi6220_divider_clock hi6220_div_clks_media[] __initdata = {
+static struct hi6220_divider_clock hi6220_div_clks_media[] = {
{ HI6220_CODEC_JPEG, "codec_jpeg_aclk", "media_pll_src", CLK_SET_RATE_PARENT, 0xcbc, 0, 4, 23, },
{ HI6220_ISP_SCLK_SRC, "isp_sclk_src", "isp_sclk_gate", CLK_SET_RATE_PARENT, 0xcbc, 8, 4, 15, },
{ HI6220_ISP_SCLK1, "isp_sclk1", "isp_sclk_gate1", CLK_SET_RATE_PARENT, 0xcbc, 24, 4, 31, },
@@ -234,28 +216,19 @@ static struct hi6220_divider_clock hi6220_div_clks_media[] __initdata = {
{ HI6220_CODEC_VPU_SRC, "codec_vpu_src", "codec_vpu_gate", CLK_SET_RATE_PARENT, 0xcc4, 24, 6, 31, },
};
-static void __init hi6220_clk_media_init(struct device_node *np)
-{
- struct hisi_clock_data *clk_data;
-
- clk_data = hisi_clk_init(np, HI6220_MEDIA_NR_CLKS);
- if (!clk_data)
- return;
-
- hisi_clk_register_gate_sep(hi6220_separated_gate_clks_media,
- ARRAY_SIZE(hi6220_separated_gate_clks_media), clk_data);
-
- hisi_clk_register_mux(hi6220_mux_clks_media,
- ARRAY_SIZE(hi6220_mux_clks_media), clk_data);
-
- hi6220_clk_register_divider(hi6220_div_clks_media,
- ARRAY_SIZE(hi6220_div_clks_media), clk_data);
-}
-CLK_OF_DECLARE_DRIVER(hi6220_clk_media, "hisilicon,hi6220-mediactrl", hi6220_clk_media_init);
-
+static const struct hisi_clocks hi6220_media_clks = {
+ .nr = HI6220_MEDIA_NR_CLKS,
+ .mux_clks = hi6220_mux_clks_media,
+ .mux_clks_num = ARRAY_SIZE(hi6220_mux_clks_media),
+ .gate_sep_clks = hi6220_separated_gate_clks_media,
+ .gate_sep_clks_num = ARRAY_SIZE(hi6220_separated_gate_clks_media),
+ .customized_clks = hi6220_div_clks_media,
+ .customized_clks_num = ARRAY_SIZE(hi6220_div_clks_media),
+ /* .clk_register_customized = hi6220_clk_register_divider, */
+};
/* clocks in pmctrl */
-static struct hisi_gate_clock hi6220_gate_clks_power[] __initdata = {
+static struct hisi_gate_clock hi6220_gate_clks_power[] = {
{ HI6220_PLL_GPU_GATE, "pll_gpu_gate", "gpupll", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x8, 0, 0, },
{ HI6220_PLL1_DDR_GATE, "pll1_ddr_gate", "ddrpll1", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x10, 0, 0, },
{ HI6220_PLL_DDR_GATE, "pll_ddr_gate", "ddrpll0", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x18, 0, 0, },
@@ -263,26 +236,19 @@ static struct hisi_gate_clock hi6220_gate_clks_power[] __initdata = {
{ HI6220_PLL0_BBP_GATE, "pll0_bbp_gate", "bbppll0", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x48, 0, 0, },
};
-static struct hi6220_divider_clock hi6220_div_clks_power[] __initdata = {
+static struct hi6220_divider_clock hi6220_div_clks_power[] = {
{ HI6220_DDRC_SRC, "ddrc_src", "ddr_sel_src", CLK_SET_RATE_PARENT, 0x5a8, 0, 4, 0, },
{ HI6220_DDRC_AXI1, "ddrc_axi1", "ddrc_src", CLK_SET_RATE_PARENT, 0x5a8, 8, 2, 0, },
};
-static void __init hi6220_clk_power_init(struct device_node *np)
-{
- struct hisi_clock_data *clk_data;
-
- clk_data = hisi_clk_init(np, HI6220_POWER_NR_CLKS);
- if (!clk_data)
- return;
-
- hisi_clk_register_gate(hi6220_gate_clks_power,
- ARRAY_SIZE(hi6220_gate_clks_power), clk_data);
-
- hi6220_clk_register_divider(hi6220_div_clks_power,
- ARRAY_SIZE(hi6220_div_clks_power), clk_data);
-}
-CLK_OF_DECLARE(hi6220_clk_power, "hisilicon,hi6220-pmctrl", hi6220_clk_power_init);
+static const struct hisi_clocks hi6220_power_clks = {
+ .nr = HI6220_POWER_NR_CLKS,
+ .gate_clks = hi6220_gate_clks_power,
+ .gate_clks_num = ARRAY_SIZE(hi6220_gate_clks_power),
+ .customized_clks = hi6220_div_clks_power,
+ .customized_clks_num = ARRAY_SIZE(hi6220_div_clks_power),
+ /* .clk_register_customized = hi6220_clk_register_divider, */
+};
/* clocks in acpu */
static const struct hisi_gate_clock hi6220_acpu_sc_gate_sep_clks[] = {
@@ -290,18 +256,37 @@ static const struct hisi_gate_clock hi6220_acpu_sc_gate_sep_clks[] = {
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0xc, 11, 0, },
};
-static void __init hi6220_clk_acpu_init(struct device_node *np)
-{
- struct hisi_clock_data *clk_data;
- int nr = ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks);
+static const struct hisi_clocks hi6220_acpu_clks = {
+ .nr = ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks),
+ .gate_sep_clks = hi6220_acpu_sc_gate_sep_clks,
+ .gate_sep_clks_num = ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks),
+};
- clk_data = hisi_clk_init(np, nr);
- if (!clk_data)
- return;
+static const struct of_device_id hi6220_clk_match_table[] = {
+ { .compatible = "hisilicon,hi6220-aoctrl",
+ .data = &hi6220_ao_clks },
+ { .compatible = "hisilicon,hi6220-sysctrl",
+ .data = &hi6220_sys_clks },
+ { .compatible = "hisilicon,hi6220-mediactrl",
+ .data = &hi6220_media_clks },
+ { .compatible = "hisilicon,hi6220-pmctrl",
+ .data = &hi6220_power_clks },
+ { .compatible = "hisilicon,hi6220-acpu-sctrl",
+ .data = &hi6220_acpu_clks },
+ { }
+};
+MODULE_DEVICE_TABLE(of, hi6220_clk_match_table);
+
+static struct platform_driver hi6220_clk_driver = {
+ .probe = hisi_clk_probe,
+ .remove = hisi_clk_remove,
+ .driver = {
+ .name = "hi6220-clock",
+ .of_match_table = hi6220_clk_match_table,
+ },
+};
- hisi_clk_register_gate_sep(hi6220_acpu_sc_gate_sep_clks,
- ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks),
- clk_data);
-}
+module_platform_driver(hi6220_clk_driver);
-CLK_OF_DECLARE(hi6220_clk_acpu, "hisilicon,hi6220-acpu-sctrl", hi6220_clk_acpu_init);
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("HiSilicon Hi6220 Clock Driver");
diff --git a/drivers/clk/hisilicon/clk-hip04.c b/drivers/clk/hisilicon/clk-hip04.c
index 785b9faf3ea5..e7d9582acc14 100644
--- a/drivers/clk/hisilicon/clk-hip04.c
+++ b/drivers/clk/hisilicon/clk-hip04.c
@@ -9,12 +9,8 @@
*/
#include <linux/kernel.h>
-#include <linux/clk-provider.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
+#include <linux/module.h>
#include <linux/of_device.h>
-#include <linux/slab.h>
#include <dt-bindings/clock/hip04-clock.h>
@@ -27,16 +23,29 @@ static struct hisi_fixed_rate_clock hip04_fixed_rate_clks[] __initdata = {
{ HIP04_CLK_168M, "clk168m", NULL, 0, 168750000, },
};
-static void __init hip04_clk_init(struct device_node *np)
-{
- struct hisi_clock_data *clk_data;
+static const struct hisi_clocks hip04_clks = {
+ .nr = ARRAY_SIZE(hip04_fixed_rate_clks),
+ .fixed_rate_clks = hip04_fixed_rate_clks,
+ .fixed_factor_clks_num = ARRAY_SIZE(hip04_fixed_rate_clks),
+};
+
+static const struct of_device_id hip04_clk_match_table[] = {
+ { .compatible = "hisilicon,hip04-clock",
+ .data = &hip04_clks },
+ { }
+};
+MODULE_DEVICE_TABLE(of, hip04_clk_match_table);
+
+static struct platform_driver hip04_clk_driver = {
+ .probe = hisi_clk_probe,
+ .remove = hisi_clk_remove,
+ .driver = {
+ .name = "hip04-clock",
+ .of_match_table = hip04_clk_match_table,
+ },
+};
- clk_data = hisi_clk_init(np, HIP04_NR_CLKS);
- if (!clk_data)
- return;
+module_platform_driver(hip04_clk_driver);
- hisi_clk_register_fixed_rate(hip04_fixed_rate_clks,
- ARRAY_SIZE(hip04_fixed_rate_clks),
- clk_data);
-}
-CLK_OF_DECLARE(hip04_clk, "hisilicon,hip04-clock", hip04_clk_init);
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("HiSilicon HiP04 Clock Driver");
diff --git a/drivers/clk/hisilicon/clk-hix5hd2.c b/drivers/clk/hisilicon/clk-hix5hd2.c
index 64bdd3f05725..f37a17649d26 100644
--- a/drivers/clk/hisilicon/clk-hix5hd2.c
+++ b/drivers/clk/hisilicon/clk-hix5hd2.c
@@ -4,13 +4,17 @@
* Copyright (c) 2014 Hisilicon Limited.
*/
-#include <linux/of_address.h>
#include <dt-bindings/clock/hix5hd2-clock.h>
+
#include <linux/slab.h>
#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+
#include "clk.h"
-static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_clks[] __initdata = {
+static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_clks[] = {
{ HIX5HD2_FIXED_1200M, "1200m", NULL, 0, 1200000000, },
{ HIX5HD2_FIXED_400M, "400m", NULL, 0, 400000000, },
{ HIX5HD2_FIXED_48M, "48m", NULL, 0, 48000000, },
@@ -43,19 +47,19 @@ static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_clks[] __initdata = {
{ HIX5HD2_FIXED_83M, "83m", NULL, 0, 83333333, },
};
-static const char *const sfc_mux_p[] __initconst = {
+static const char *const sfc_mux_p[] = {
"24m", "150m", "200m", "100m", "75m", };
static u32 sfc_mux_table[] = {0, 4, 5, 6, 7};
-static const char *const sdio_mux_p[] __initconst = {
+static const char *const sdio_mux_p[] = {
"75m", "100m", "50m", "15m", };
static u32 sdio_mux_table[] = {0, 1, 2, 3};
-static const char *const fephy_mux_p[] __initconst = { "25m", "125m"};
+static const char *const fephy_mux_p[] = { "25m", "125m"};
static u32 fephy_mux_table[] = {0, 1};
-static struct hisi_mux_clock hix5hd2_mux_clks[] __initdata = {
+static struct hisi_mux_clock hix5hd2_mux_clks[] = {
{ HIX5HD2_SFC_MUX, "sfc_mux", sfc_mux_p, ARRAY_SIZE(sfc_mux_p),
CLK_SET_RATE_PARENT, 0x5c, 8, 3, 0, sfc_mux_table, },
{ HIX5HD2_MMC_MUX, "mmc_mux", sdio_mux_p, ARRAY_SIZE(sdio_mux_p),
@@ -67,7 +71,7 @@ static struct hisi_mux_clock hix5hd2_mux_clks[] __initdata = {
CLK_SET_RATE_PARENT, 0x120, 8, 2, 0, fephy_mux_table, },
};
-static struct hisi_gate_clock hix5hd2_gate_clks[] __initdata = {
+static struct hisi_gate_clock hix5hd2_gate_clks[] = {
/* sfc */
{ HIX5HD2_SFC_CLK, "clk_sfc", "sfc_mux",
CLK_SET_RATE_PARENT, 0x5c, 0, 0, },
@@ -153,7 +157,7 @@ struct hix5hd2_clk_complex {
u32 phy_rst_mask;
};
-static struct hix5hd2_complex_clock hix5hd2_complex_clks[] __initdata = {
+static struct hix5hd2_complex_clock hix5hd2_complex_clks[] = {
{"clk_mac0", "clk_fephy", HIX5HD2_MAC0_CLK,
0xcc, 0xa, 0x500, 0x120, 0, 0x10, TYPE_ETHER},
{"clk_mac1", "clk_fwd_sys", HIX5HD2_MAC1_CLK,
@@ -249,10 +253,11 @@ static const struct clk_ops clk_complex_ops = {
.disable = clk_complex_disable,
};
-static void __init
-hix5hd2_clk_register_complex(struct hix5hd2_complex_clock *clks, int nums,
+static int
+hix5hd2_clk_register_complex(struct device *dev, const void *clocks, int nums,
struct hisi_clock_data *data)
{
+ const struct hix5hd2_complex_clock *clks = clocks;
void __iomem *base = data->base;
int i;
@@ -263,7 +268,7 @@ hix5hd2_clk_register_complex(struct hix5hd2_complex_clock *clks, int nums,
p_clk = kzalloc(sizeof(*p_clk), GFP_KERNEL);
if (!p_clk)
- return;
+ return -ENOMEM;
init.name = clks[i].name;
if (clks[i].type == TYPE_ETHER)
@@ -289,31 +294,45 @@ hix5hd2_clk_register_complex(struct hix5hd2_complex_clock *clks, int nums,
kfree(p_clk);
pr_err("%s: failed to register clock %s\n",
__func__, clks[i].name);
- continue;
+ return PTR_ERR(p_clk);
}
data->clk_data.clks[clks[i].id] = clk;
}
-}
-static void __init hix5hd2_clk_init(struct device_node *np)
-{
- struct hisi_clock_data *clk_data;
-
- clk_data = hisi_clk_init(np, HIX5HD2_NR_CLKS);
- if (!clk_data)
- return;
-
- hisi_clk_register_fixed_rate(hix5hd2_fixed_rate_clks,
- ARRAY_SIZE(hix5hd2_fixed_rate_clks),
- clk_data);
- hisi_clk_register_mux(hix5hd2_mux_clks, ARRAY_SIZE(hix5hd2_mux_clks),
- clk_data);
- hisi_clk_register_gate(hix5hd2_gate_clks,
- ARRAY_SIZE(hix5hd2_gate_clks), clk_data);
- hix5hd2_clk_register_complex(hix5hd2_complex_clks,
- ARRAY_SIZE(hix5hd2_complex_clks),
- clk_data);
+ return 0;
}
-CLK_OF_DECLARE(hix5hd2_clk, "hisilicon,hix5hd2-clock", hix5hd2_clk_init);
+static const struct hisi_clocks hix5hd2_clks = {
+ .nr = HIX5HD2_NR_CLKS,
+ .fixed_rate_clks = hix5hd2_fixed_rate_clks,
+ .fixed_factor_clks_num = ARRAY_SIZE(hix5hd2_fixed_rate_clks),
+ .mux_clks = hix5hd2_mux_clks,
+ .mux_clks_num = ARRAY_SIZE(hix5hd2_mux_clks),
+ .gate_clks = hix5hd2_gate_clks,
+ .gate_clks_num = ARRAY_SIZE(hix5hd2_gate_clks),
+ .customized_clks = hix5hd2_complex_clks,
+ .customized_clks_num = ARRAY_SIZE(hix5hd2_complex_clks),
+ .clk_register_customized = hix5hd2_clk_register_complex,
+};
+
+static const struct of_device_id hix5hd2_clk_match_table[] = {
+ { .compatible = "hisilicon,hix5hd2-clock",
+ .data = &hix5hd2_clks },
+ { }
+};
+MODULE_DEVICE_TABLE(of, hix5hd2_clk_match_table);
+
+static struct platform_driver hix5hd2_clk_driver = {
+ .probe = hisi_clk_probe,
+ .remove = hisi_clk_remove,
+ .driver = {
+ .name = "hix5hd2-clock",
+ .of_match_table = hix5hd2_clk_match_table,
+ },
+};
+
+module_platform_driver(hix5hd2_clk_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("HiSilicon Hix5hd2 Clock Driver");
--
2.39.2
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v2 3/4] clk: hisilicon: Convert to platform driver
2023-03-29 7:50 ` [PATCH v2 3/4] clk: hisilicon: Convert to platform driver David Yang
@ 2023-04-05 21:08 ` Stephen Boyd
0 siblings, 0 replies; 9+ messages in thread
From: Stephen Boyd @ 2023-04-05 21:08 UTC (permalink / raw)
To: David Yang, linux-clk; +Cc: David Yang, Michael Turquette, linux-kernel
Quoting David Yang (2023-03-29 00:50:52)
> - clk_data);
> - hisi_clk_register_fixed_factor(hi3620_fixed_factor_clks,
> - ARRAY_SIZE(hi3620_fixed_factor_clks),
> - clk_data);
> - hisi_clk_register_mux(hi3620_mux_clks, ARRAY_SIZE(hi3620_mux_clks),
> - clk_data);
> - hisi_clk_register_divider(hi3620_div_clks, ARRAY_SIZE(hi3620_div_clks),
> - clk_data);
> - hisi_clk_register_gate_sep(hi3620_separated_gate_clks,
> - ARRAY_SIZE(hi3620_separated_gate_clks),
> - clk_data);
> -}
> -CLK_OF_DECLARE(hi3620_clk, "hisilicon,hi3620-clock", hi3620_clk_init);
> +static const struct hisi_clocks hi3620_clks = {
> + .nr = HI3620_NR_CLKS,
Can this simply be calculated by adding together all the _num members?
> + .fixed_rate_clks = hi3620_fixed_rate_clks,
> + .fixed_rate_clks_num = ARRAY_SIZE(hi3620_fixed_rate_clks),
> + .fixed_factor_clks = hi3620_fixed_factor_clks,
> + .fixed_factor_clks_num = ARRAY_SIZE(hi3620_fixed_factor_clks),
> + .mux_clks = hi3620_mux_clks,
> + .mux_clks_num = ARRAY_SIZE(hi3620_mux_clks),
> + .divider_clks = hi3620_div_clks
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 4/4] clk: hisilicon: Migrate devm APIs
2023-03-29 7:50 [PATCH v2 0/4] clk: hisilicon: Migrate devm APIs David Yang
` (2 preceding siblings ...)
2023-03-29 7:50 ` [PATCH v2 3/4] clk: hisilicon: Convert to platform driver David Yang
@ 2023-03-29 7:50 ` David Yang
2023-04-05 19:39 ` [PATCH v2 0/4] " Stephen Boyd
4 siblings, 0 replies; 9+ messages in thread
From: David Yang @ 2023-03-29 7:50 UTC (permalink / raw)
To: linux-clk
Cc: David Yang, Michael Turquette, Stephen Boyd, linux-kernel,
Conor Dooley, Nick Alcock
Migrates devm APIs for HiSilicon clock drivers.
Signed-off-by: David Yang <mmyangfl@gmail.com>
---
drivers/clk/hisilicon/clk-hi3559a.c | 29 +-
drivers/clk/hisilicon/clk-hi3620.c | 28 +-
drivers/clk/hisilicon/clk-hi6220-stub.c | 9 +-
drivers/clk/hisilicon/clk-hi6220.c | 13 +-
drivers/clk/hisilicon/clk-hisi-phase.c | 13 +-
drivers/clk/hisilicon/clk-hix5hd2.c | 15 +-
drivers/clk/hisilicon/clk.c | 411 +++++++---------------
drivers/clk/hisilicon/clk.h | 97 ++---
drivers/clk/hisilicon/clkdivider-hi6220.c | 24 +-
drivers/clk/hisilicon/clkgate-separated.c | 26 +-
10 files changed, 263 insertions(+), 402 deletions(-)
diff --git a/drivers/clk/hisilicon/clk-hi3559a.c b/drivers/clk/hisilicon/clk-hi3559a.c
index d641b2a759dd..926a7c211978 100644
--- a/drivers/clk/hisilicon/clk-hi3559a.c
+++ b/drivers/clk/hisilicon/clk-hi3559a.c
@@ -457,17 +457,16 @@ hisi_clk_register_pll(struct device *dev, const void *clocks,
{
const struct hi3559av100_pll_clock *clks = clocks;
void __iomem *base = data->base;
- struct hi3559av100_clk_pll *p_clk = NULL;
- struct clk *clk = NULL;
+ struct hi3559av100_clk_pll *p_clk;
struct clk_init_data init;
int i;
-
- p_clk = devm_kzalloc(dev, sizeof(*p_clk) * nums, GFP_KERNEL);
-
- if (!p_clk)
- return -ENOMEM;
+ int ret;
for (i = 0; i < nums; i++) {
+ p_clk = devm_kzalloc(dev, sizeof(*p_clk), GFP_KERNEL);
+ if (!p_clk)
+ return -ENOMEM;
+
init.name = clks[i].name;
init.flags = 0;
init.parent_names =
@@ -490,16 +489,14 @@ hisi_clk_register_pll(struct device *dev, const void *clocks,
p_clk->refdiv_width = clks[i].refdiv_width;
p_clk->hw.init = &init;
- clk = clk_register(NULL, &p_clk->hw);
- if (IS_ERR(clk)) {
- devm_kfree(dev, p_clk);
+ ret = devm_clk_hw_register(dev, &p_clk->hw);
+ if (ret) {
dev_err(dev, "%s: failed to register clock %s\n",
- __func__, clks[i].name);
- return PTR_ERR(clk);
+ __func__, clks[i].name);
+ return ret;
}
- data->clk_data.clks[clks[i].id] = clk;
- p_clk++;
+ data->clk_data->hws[clks[i].id] = &p_clk->hw;
}
return 0;
@@ -628,7 +625,7 @@ static int hi3559av100_shub_default_clk_set(struct device *dev, struct hisi_cloc
void __iomem *crg_base;
unsigned int val;
- crg_base = ioremap(CRG_BASE_ADDR, SZ_4K);
+ crg_base = devm_ioremap(dev, CRG_BASE_ADDR, SZ_4K);
/* SSP: 192M/2 */
val = readl_relaxed(crg_base + 0x20);
@@ -640,7 +637,7 @@ static int hi3559av100_shub_default_clk_set(struct device *dev, struct hisi_cloc
val |= (0x1 << 28);
writel_relaxed(val, crg_base + 0x1C);
- iounmap(crg_base);
+ devm_iounmap(dev, crg_base);
crg_base = NULL;
return 0;
diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk-hi3620.c
index 1eacf77b0d8c..44dd0c0a7d32 100644
--- a/drivers/clk/hisilicon/clk-hi3620.c
+++ b/drivers/clk/hisilicon/clk-hi3620.c
@@ -11,12 +11,10 @@
#include <linux/kernel.h>
#include <linux/clk-provider.h>
+#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
#include <linux/of_device.h>
-#include <linux/slab.h>
#include <dt-bindings/clock/hi3620-clock.h>
@@ -399,15 +397,15 @@ static const struct clk_ops clk_mmc_ops = {
.recalc_rate = mmc_clk_recalc_rate,
};
-static struct clk *
+static struct clk_hw *
clk_register_hisi_mmc(struct device *dev, const struct hisi_mmc_clock *mmc_clk,
void __iomem *base)
{
struct clk_mmc *mclk;
- struct clk *clk;
struct clk_init_data init;
+ int ret;
- mclk = kzalloc(sizeof(*mclk), GFP_KERNEL);
+ mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL);
if (!mclk)
return ERR_PTR(-ENOMEM);
@@ -431,27 +429,31 @@ clk_register_hisi_mmc(struct device *dev, const struct hisi_mmc_clock *mmc_clk,
mclk->sam_off = mmc_clk->sam_off;
mclk->sam_bits = mmc_clk->sam_bits;
- clk = clk_register(NULL, &mclk->hw);
- if (WARN_ON(IS_ERR(clk)))
- kfree(mclk);
- return clk;
+ ret = devm_clk_hw_register(dev, &mclk->hw);
+ if (ret) {
+ dev_err(dev, "%s: failed to register clock %s\n",
+ __func__, init.name);
+ return ERR_PTR(ret);
+ }
+
+ return &mclk->hw;
}
static int hisi_register_clk_mmc(struct device *dev, const void *clocks,
int nums, struct hisi_clock_data *data)
{
const struct hisi_mmc_clock *clks = clocks;
- struct clk *clk;
int i;
for (i = 0; i < nums; i++) {
- clk = clk_register_hisi_mmc(dev, &clks[i], data->base);
+ struct clk_hw *clk = clk_register_hisi_mmc(dev, &clks[i], data->base);
+
if (IS_ERR(clk)) {
pr_err("%s: failed to register clock %s\n",
__func__, clks[i].name);
return PTR_ERR(clk);
}
- data->clk_data.clks[clks[i].id] = clk;
+ data->clk_data->hws[clks[i].id] = clk;
}
return 0;
diff --git a/drivers/clk/hisilicon/clk-hi6220-stub.c b/drivers/clk/hisilicon/clk-hi6220-stub.c
index 4fdee4424d82..dd996a43958e 100644
--- a/drivers/clk/hisilicon/clk-hi6220-stub.c
+++ b/drivers/clk/hisilicon/clk-hi6220-stub.c
@@ -195,7 +195,6 @@ static int hi6220_stub_clk_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct clk_init_data init;
struct hi6220_stub_clk *stub_clk;
- struct clk *clk;
struct device_node *np = pdev->dev.of_node;
int ret;
@@ -233,11 +232,11 @@ static int hi6220_stub_clk_probe(struct platform_device *pdev)
init.num_parents = 0;
init.flags = 0;
- clk = devm_clk_register(dev, &stub_clk->hw);
- if (IS_ERR(clk))
- return PTR_ERR(clk);
+ ret = devm_clk_hw_register(dev, &stub_clk->hw);
+ if (ret)
+ return ret;
- ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
+ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &stub_clk->hw);
if (ret) {
dev_err(dev, "failed to register OF clock provider\n");
return ret;
diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c
index cdc17f82ce2d..d37a3633f8ae 100644
--- a/drivers/clk/hisilicon/clk-hi6220.c
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -16,6 +16,13 @@
#include "clk.h"
+static int
+hi6220_clk_register_divider_stub(struct device *dev, const void *clks,
+ int num, struct hisi_clock_data *data)
+{
+ return hi6220_clk_register_divider(dev, clks, num, data);
+}
+
/* clocks in AO (always on) controller */
static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] = {
{ HI6220_REF32K, "ref32k", NULL, 0, 32764, },
@@ -176,7 +183,7 @@ static const struct hisi_clocks hi6220_sys_clks = {
.gate_sep_clks_num = ARRAY_SIZE(hi6220_separated_gate_clks_sys),
.customized_clks = hi6220_div_clks_sys,
.customized_clks_num = ARRAY_SIZE(hi6220_div_clks_sys),
- /* .clk_register_customized = hi6220_clk_register_divider, */
+ .clk_register_customized = hi6220_clk_register_divider_stub,
};
/* clocks in media controller */
@@ -224,7 +231,7 @@ static const struct hisi_clocks hi6220_media_clks = {
.gate_sep_clks_num = ARRAY_SIZE(hi6220_separated_gate_clks_media),
.customized_clks = hi6220_div_clks_media,
.customized_clks_num = ARRAY_SIZE(hi6220_div_clks_media),
- /* .clk_register_customized = hi6220_clk_register_divider, */
+ .clk_register_customized = hi6220_clk_register_divider_stub,
};
/* clocks in pmctrl */
@@ -247,7 +254,7 @@ static const struct hisi_clocks hi6220_power_clks = {
.gate_clks_num = ARRAY_SIZE(hi6220_gate_clks_power),
.customized_clks = hi6220_div_clks_power,
.customized_clks_num = ARRAY_SIZE(hi6220_div_clks_power),
- /* .clk_register_customized = hi6220_clk_register_divider, */
+ .clk_register_customized = hi6220_clk_register_divider_stub,
};
/* clocks in acpu */
diff --git a/drivers/clk/hisilicon/clk-hisi-phase.c b/drivers/clk/hisilicon/clk-hisi-phase.c
index ba6afad66a2b..15a23dd6edb1 100644
--- a/drivers/clk/hisilicon/clk-hisi-phase.c
+++ b/drivers/clk/hisilicon/clk-hisi-phase.c
@@ -5,11 +5,11 @@
* Simple HiSilicon phase clock implementation.
*/
+#include <linux/device.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
-#include <linux/slab.h>
#include "clk.h"
@@ -90,12 +90,13 @@ static const struct clk_ops clk_phase_ops = {
.set_phase = hisi_clk_set_phase,
};
-struct clk *clk_register_hisi_phase(struct device *dev,
+struct clk_hw *devm_clk_hw_register_hisi_phase(struct device *dev,
const struct hisi_phase_clock *clks,
void __iomem *base, spinlock_t *lock)
{
struct clk_hisi_phase *phase;
struct clk_init_data init;
+ int ret;
phase = devm_kzalloc(dev, sizeof(struct clk_hisi_phase), GFP_KERNEL);
if (!phase)
@@ -116,6 +117,10 @@ struct clk *clk_register_hisi_phase(struct device *dev,
phase->phase_num = clks->phase_num;
phase->hw.init = &init;
- return devm_clk_register(dev, &phase->hw);
+ ret = devm_clk_hw_register(dev, &phase->hw);
+ if (ret)
+ return ERR_PTR(ret);
+
+ return &phase->hw;
}
-EXPORT_SYMBOL_GPL(clk_register_hisi_phase);
+EXPORT_SYMBOL_GPL(devm_clk_hw_register_hisi_phase);
diff --git a/drivers/clk/hisilicon/clk-hix5hd2.c b/drivers/clk/hisilicon/clk-hix5hd2.c
index f37a17649d26..7c170d81a75b 100644
--- a/drivers/clk/hisilicon/clk-hix5hd2.c
+++ b/drivers/clk/hisilicon/clk-hix5hd2.c
@@ -6,7 +6,7 @@
#include <dt-bindings/clock/hix5hd2-clock.h>
-#include <linux/slab.h>
+#include <linux/device.h>
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/module.h>
@@ -260,13 +260,13 @@ hix5hd2_clk_register_complex(struct device *dev, const void *clocks, int nums,
const struct hix5hd2_complex_clock *clks = clocks;
void __iomem *base = data->base;
int i;
+ int ret;
for (i = 0; i < nums; i++) {
struct hix5hd2_clk_complex *p_clk;
- struct clk *clk;
struct clk_init_data init;
- p_clk = kzalloc(sizeof(*p_clk), GFP_KERNEL);
+ p_clk = devm_kzalloc(dev, sizeof(*p_clk), GFP_KERNEL);
if (!p_clk)
return -ENOMEM;
@@ -289,15 +289,14 @@ hix5hd2_clk_register_complex(struct device *dev, const void *clocks, int nums,
p_clk->phy_rst_mask = clks[i].phy_rst_mask;
p_clk->hw.init = &init;
- clk = clk_register(NULL, &p_clk->hw);
- if (IS_ERR(clk)) {
- kfree(p_clk);
+ ret = devm_clk_hw_register(dev, &p_clk->hw);
+ if (ret) {
pr_err("%s: failed to register clock %s\n",
__func__, clks[i].name);
- return PTR_ERR(p_clk);
+ return ret;
}
- data->clk_data.clks[clks[i].id] = clk;
+ data->clk_data->hws[clks[i].id] = &p_clk->hw;
}
return 0;
diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c
index 96bbc09e7d45..9a5d530c772b 100644
--- a/drivers/clk/hisilicon/clk.c
+++ b/drivers/clk/hisilicon/clk.c
@@ -4,6 +4,7 @@
*
* Copyright (c) 2012-2013 Hisilicon Limited.
* Copyright (c) 2012-2013 Linaro Limited.
+ * Copyright (c) 2023 David Yang
*
* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
* Xin Li <li.xin@linaro.org>
@@ -13,6 +14,8 @@
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/errno.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
@@ -23,67 +26,44 @@
static DEFINE_SPINLOCK(hisi_clk_lock);
-struct hisi_clock_data *hisi_clk_alloc(struct platform_device *pdev,
- int nr_clks)
+struct hisi_clock_data *hisi_clk_init(struct device_node *np, int nr)
{
- struct hisi_clock_data *clk_data;
- struct resource *res;
- struct clk **clk_table;
-
- clk_data = devm_kmalloc(&pdev->dev, sizeof(*clk_data), GFP_KERNEL);
- if (!clk_data)
- return NULL;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res)
- return NULL;
- clk_data->base = devm_ioremap(&pdev->dev,
- res->start, resource_size(res));
- if (!clk_data->base)
- return NULL;
-
- clk_table = devm_kmalloc_array(&pdev->dev, nr_clks,
- sizeof(*clk_table),
- GFP_KERNEL);
- if (!clk_table)
- return NULL;
-
- clk_data->clk_data.clks = clk_table;
- clk_data->clk_data.clk_num = nr_clks;
-
- return clk_data;
-}
-EXPORT_SYMBOL_GPL(hisi_clk_alloc);
-
-struct hisi_clock_data *hisi_clk_init(struct device_node *np,
- int nr_clks)
-{
- struct hisi_clock_data *clk_data;
- struct clk **clk_table;
void __iomem *base;
+ struct hisi_clock_data *data;
+ int ret;
+ int i;
base = of_iomap(np, 0);
if (!base) {
pr_err("%s: failed to map clock registers\n", __func__);
- goto err;
+ return NULL;
}
- clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
- if (!clk_data)
- goto err;
+ data = kmalloc(sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return NULL;
- clk_data->base = base;
- clk_table = kcalloc(nr_clks, sizeof(*clk_table), GFP_KERNEL);
- if (!clk_table)
+ data->clk_data = kzalloc(sizeof(*data->clk_data) + nr * sizeof(data->clk_data->hws[0]),
+ GFP_KERNEL);
+ if (!data->clk_data)
goto err_data;
- clk_data->clk_data.clks = clk_table;
- clk_data->clk_data.clk_num = nr_clks;
- of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);
- return clk_data;
+ ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, data->clk_data);
+ if (ret)
+ goto err_clk;
+
+ data->base = base;
+ data->clks = NULL;
+ data->clk_data->num = nr;
+ for (i = 0; i < nr; i++)
+ data->clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
+
+ return data;
+
+err_clk:
+ kfree(data->clk_data);
err_data:
- kfree(clk_data);
-err:
+ kfree(data);
return NULL;
}
EXPORT_SYMBOL_GPL(hisi_clk_init);
@@ -92,312 +72,171 @@ void hisi_clk_free(struct device_node *np, struct hisi_clock_data *data)
{
if (data->clks) {
if (data->clks->fixed_rate_clks_num)
- hisi_clk_unregister_fixed_rate(data->clks->fixed_rate_clks,
- data->clks->fixed_rate_clks_num,
- data);
+ hisi_clk_unregister_fixed_rate(data);
if (data->clks->fixed_factor_clks_num)
- hisi_clk_unregister_fixed_factor(data->clks->fixed_factor_clks,
- data->clks->fixed_factor_clks_num,
- data);
+ hisi_clk_unregister_fixed_factor(data);
}
of_clk_del_provider(np);
- kfree(data->clk_data.clks);
+ kfree(data->clk_data);
kfree(data);
}
EXPORT_SYMBOL_GPL(hisi_clk_free);
int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *clks,
- int nums, struct hisi_clock_data *data)
+ int num, struct hisi_clock_data *data)
{
- struct clk *clk;
+ struct clk_hw *clk;
int i;
- for (i = 0; i < nums; i++) {
- clk = clk_register_fixed_rate(NULL, clks[i].name,
- clks[i].parent_name,
- clks[i].flags,
- clks[i].fixed_rate);
+ for (i = 0; i < num; i++) {
+ const struct hisi_fixed_rate_clock *p_clk = &clks[i];
+
+ clk = clk_hw_register_fixed_rate(NULL, p_clk->name, p_clk->parent_name,
+ p_clk->flags, p_clk->fixed_rate);
+
if (IS_ERR(clk)) {
pr_err("%s: failed to register clock %s\n",
- __func__, clks[i].name);
+ __func__, p_clk->name);
goto err;
}
- data->clk_data.clks[clks[i].id] = clk;
+
+ data->clk_data->hws[p_clk->id] = clk;
}
return 0;
err:
while (i--)
- clk_unregister_fixed_rate(data->clk_data.clks[clks[i].id]);
-
+ clk_hw_unregister_fixed_rate(data->clk_data->hws[clks[i].id]);
return PTR_ERR(clk);
}
EXPORT_SYMBOL_GPL(hisi_clk_register_fixed_rate);
int hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *clks,
- int nums,
- struct hisi_clock_data *data)
+ int num, struct hisi_clock_data *data)
{
- struct clk *clk;
+ struct clk_hw *clk;
int i;
- for (i = 0; i < nums; i++) {
- clk = clk_register_fixed_factor(NULL, clks[i].name,
- clks[i].parent_name,
- clks[i].flags, clks[i].mult,
- clks[i].div);
- if (IS_ERR(clk)) {
- pr_err("%s: failed to register clock %s\n",
- __func__, clks[i].name);
- goto err;
- }
- data->clk_data.clks[clks[i].id] = clk;
- }
-
- return 0;
+ for (i = 0; i < num; i++) {
+ const struct hisi_fixed_factor_clock *p_clk = &clks[i];
-err:
- while (i--)
- clk_unregister_fixed_factor(data->clk_data.clks[clks[i].id]);
-
- return PTR_ERR(clk);
-}
-EXPORT_SYMBOL_GPL(hisi_clk_register_fixed_factor);
+ clk = clk_hw_register_fixed_factor(NULL, p_clk->name, p_clk->parent_name,
+ p_clk->flags, p_clk->mult, p_clk->div);
-int hisi_clk_register_mux(const struct hisi_mux_clock *clks,
- int nums, struct hisi_clock_data *data)
-{
- struct clk *clk;
- void __iomem *base = data->base;
- int i;
-
- for (i = 0; i < nums; i++) {
- u32 mask = BIT(clks[i].width) - 1;
-
- clk = clk_register_mux_table(NULL, clks[i].name,
- clks[i].parent_names,
- clks[i].num_parents, clks[i].flags,
- base + clks[i].offset, clks[i].shift,
- mask, clks[i].mux_flags,
- clks[i].table, &hisi_clk_lock);
if (IS_ERR(clk)) {
pr_err("%s: failed to register clock %s\n",
- __func__, clks[i].name);
+ __func__, p_clk->name);
goto err;
}
- if (clks[i].alias)
- clk_register_clkdev(clk, clks[i].alias, NULL);
-
- data->clk_data.clks[clks[i].id] = clk;
+ data->clk_data->hws[p_clk->id] = clk;
}
return 0;
err:
while (i--)
- clk_unregister_mux(data->clk_data.clks[clks[i].id]);
-
+ clk_hw_unregister_fixed_rate(data->clk_data->hws[clks[i].id]);
return PTR_ERR(clk);
}
-EXPORT_SYMBOL_GPL(hisi_clk_register_mux);
+EXPORT_SYMBOL_GPL(hisi_clk_register_fixed_factor);
+
+#define hisi_clk_register_fn(fn, type, stmt) \
+int fn(struct device *dev, const struct type *clks, \
+ int num, struct hisi_clock_data *data) \
+{ \
+ void __iomem *base = data->base; \
+ int i; \
+\
+ for (i = 0; i < num; i++) { \
+ const struct type *p_clk = &clks[i]; \
+ struct clk_hw *clk = stmt; \
+\
+ if (IS_ERR(clk)) { \
+ pr_err("%s: failed to register clock %s\n", \
+ __func__, p_clk->name); \
+ return PTR_ERR(clk); \
+ } \
+\
+ if (p_clk->alias) \
+ clk_hw_register_clkdev(clk, p_clk->alias, NULL); \
+\
+ data->clk_data->hws[p_clk->id] = clk; \
+ } \
+\
+ return 0; \
+} \
+EXPORT_SYMBOL_GPL(fn);
+
+hisi_clk_register_fn(hisi_clk_register_mux, hisi_mux_clock,
+ __devm_clk_hw_register_mux(dev, NULL, p_clk->name,
+ p_clk->num_parents, p_clk->parent_names, NULL, NULL,
+ p_clk->flags, base + p_clk->offset, p_clk->shift, BIT(p_clk->width) - 1,
+ p_clk->mux_flags, p_clk->table, &hisi_clk_lock))
int hisi_clk_register_phase(struct device *dev,
const struct hisi_phase_clock *clks,
- int nums, struct hisi_clock_data *data)
+ int num, struct hisi_clock_data *data)
{
void __iomem *base = data->base;
- struct clk *clk;
int i;
- for (i = 0; i < nums; i++) {
- clk = clk_register_hisi_phase(dev, &clks[i], base,
- &hisi_clk_lock);
+ for (i = 0; i < num; i++) {
+ const struct hisi_phase_clock *p_clk = &clks[i];
+ struct clk_hw *clk = devm_clk_hw_register_hisi_phase(dev,
+ p_clk, base, &hisi_clk_lock);
+
if (IS_ERR(clk)) {
pr_err("%s: failed to register clock %s\n", __func__,
- clks[i].name);
+ p_clk->name);
return PTR_ERR(clk);
}
- data->clk_data.clks[clks[i].id] = clk;
+ data->clk_data->hws[p_clk->id] = clk;
}
return 0;
}
EXPORT_SYMBOL_GPL(hisi_clk_register_phase);
-int hisi_clk_register_divider(const struct hisi_divider_clock *clks,
- int nums, struct hisi_clock_data *data)
-{
- struct clk *clk;
- void __iomem *base = data->base;
- int i;
-
- for (i = 0; i < nums; i++) {
- clk = clk_register_divider_table(NULL, clks[i].name,
- clks[i].parent_name,
- clks[i].flags,
- base + clks[i].offset,
- clks[i].shift, clks[i].width,
- clks[i].div_flags,
- clks[i].table,
- &hisi_clk_lock);
- if (IS_ERR(clk)) {
- pr_err("%s: failed to register clock %s\n",
- __func__, clks[i].name);
- goto err;
- }
-
- if (clks[i].alias)
- clk_register_clkdev(clk, clks[i].alias, NULL);
-
- data->clk_data.clks[clks[i].id] = clk;
- }
-
- return 0;
-
-err:
- while (i--)
- clk_unregister_divider(data->clk_data.clks[clks[i].id]);
-
- return PTR_ERR(clk);
-}
-EXPORT_SYMBOL_GPL(hisi_clk_register_divider);
-
-int hisi_clk_register_gate(const struct hisi_gate_clock *clks,
- int nums, struct hisi_clock_data *data)
-{
- struct clk *clk;
- void __iomem *base = data->base;
- int i;
-
- for (i = 0; i < nums; i++) {
- clk = clk_register_gate(NULL, clks[i].name,
- clks[i].parent_name,
- clks[i].flags,
- base + clks[i].offset,
- clks[i].bit_idx,
- clks[i].gate_flags,
- &hisi_clk_lock);
- if (IS_ERR(clk)) {
- pr_err("%s: failed to register clock %s\n",
- __func__, clks[i].name);
- goto err;
- }
-
- if (clks[i].alias)
- clk_register_clkdev(clk, clks[i].alias, NULL);
-
- data->clk_data.clks[clks[i].id] = clk;
- }
-
- return 0;
-
-err:
- while (i--)
- clk_unregister_gate(data->clk_data.clks[clks[i].id]);
-
- return PTR_ERR(clk);
-}
-EXPORT_SYMBOL_GPL(hisi_clk_register_gate);
-
-void hisi_clk_register_gate_sep(const struct hisi_gate_clock *clks,
- int nums, struct hisi_clock_data *data)
-{
- struct clk *clk;
- void __iomem *base = data->base;
- int i;
-
- for (i = 0; i < nums; i++) {
- clk = hisi_register_clkgate_sep(NULL, clks[i].name,
- clks[i].parent_name,
- clks[i].flags,
- base + clks[i].offset,
- clks[i].bit_idx,
- clks[i].gate_flags,
- &hisi_clk_lock);
- if (IS_ERR(clk)) {
- pr_err("%s: failed to register clock %s\n",
- __func__, clks[i].name);
- continue;
- }
-
- if (clks[i].alias)
- clk_register_clkdev(clk, clks[i].alias, NULL);
-
- data->clk_data.clks[clks[i].id] = clk;
- }
-}
-EXPORT_SYMBOL_GPL(hisi_clk_register_gate_sep);
-
-void __init hi6220_clk_register_divider(const struct hi6220_divider_clock *clks,
- int nums, struct hisi_clock_data *data)
-{
- struct clk *clk;
- void __iomem *base = data->base;
- int i;
-
- for (i = 0; i < nums; i++) {
- clk = hi6220_register_clkdiv(NULL, clks[i].name,
- clks[i].parent_name,
- clks[i].flags,
- base + clks[i].offset,
- clks[i].shift,
- clks[i].width,
- clks[i].mask_bit,
- &hisi_clk_lock);
- if (IS_ERR(clk)) {
- pr_err("%s: failed to register clock %s\n",
- __func__, clks[i].name);
- continue;
- }
-
- if (clks[i].alias)
- clk_register_clkdev(clk, clks[i].alias, NULL);
-
- data->clk_data.clks[clks[i].id] = clk;
- }
-}
+hisi_clk_register_fn(hisi_clk_register_divider, hisi_divider_clock,
+ devm_clk_hw_register_divider_table(dev, p_clk->name, p_clk->parent_name,
+ p_clk->flags, base + p_clk->offset, p_clk->shift, p_clk->width,
+ p_clk->div_flags, p_clk->table, &hisi_clk_lock))
+hisi_clk_register_fn(hisi_clk_register_gate, hisi_gate_clock,
+ devm_clk_hw_register_gate(dev, p_clk->name, p_clk->parent_name,
+ p_clk->flags, base + p_clk->offset, p_clk->bit_idx,
+ p_clk->gate_flags, &hisi_clk_lock))
+hisi_clk_register_fn(hisi_clk_register_gate_sep, hisi_gate_clock,
+ devm_clk_hw_register_hisi_gate_sep(dev, p_clk->name, p_clk->parent_name,
+ p_clk->flags, base + p_clk->offset, p_clk->bit_idx,
+ p_clk->gate_flags, &hisi_clk_lock))
+hisi_clk_register_fn(hi6220_clk_register_divider, hi6220_divider_clock,
+ devm_clk_hw_register_hi6220_divider(dev, p_clk->name, p_clk->parent_name,
+ p_clk->flags, base + p_clk->offset, p_clk->shift, p_clk->width,
+ p_clk->mask_bit, &hisi_clk_lock))
int hisi_clk_register(struct device *dev, const struct hisi_clocks *clks,
struct hisi_clock_data *data)
{
int ret;
- if (clks->mux_clks_num) {
- ret = hisi_clk_register_mux(clks->mux_clks,
- clks->mux_clks_num, data);
- if (ret)
- return ret;
- }
-
- if (clks->phase_clks_num) {
- ret = hisi_clk_register_phase(dev, clks->phase_clks,
- clks->phase_clks_num, data);
- if (ret)
- return ret;
- }
-
- if (clks->divider_clks_num) {
- ret = hisi_clk_register_divider(clks->divider_clks,
- clks->divider_clks_num, data);
- if (ret)
- return ret;
- }
-
- if (clks->gate_clks_num) {
- ret = hisi_clk_register_gate(clks->gate_clks,
- clks->gate_clks_num, data);
- if (ret)
- return ret;
- }
-
- if (clks->gate_sep_clks_num) {
- hisi_clk_register_gate_sep(clks->gate_sep_clks,
- clks->gate_sep_clks_num, data);
- }
+#define do_hisi_clk_register(type) do { \
+ if (clks->type##_clks_num) { \
+ ret = hisi_clk_register_##type(dev, clks->type##_clks, \
+ clks->type##_clks_num, data); \
+ if (ret) \
+ return ret; \
+ } \
+} while (0)
+
+ do_hisi_clk_register(mux);
+ do_hisi_clk_register(phase);
+ do_hisi_clk_register(divider);
+ do_hisi_clk_register(gate);
+ do_hisi_clk_register(gate_sep);
if (clks->clk_register_customized && clks->customized_clks_num) {
ret = clks->clk_register_customized(dev, clks->customized_clks,
diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h
index def94498e14d..44fafab996bf 100644
--- a/drivers/clk/hisilicon/clk.h
+++ b/drivers/clk/hisilicon/clk.h
@@ -4,6 +4,7 @@
*
* Copyright (c) 2012-2013 Hisilicon Limited.
* Copyright (c) 2012-2013 Linaro Limited.
+ * Copyright (c) 2023 David Yang
*
* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
* Xin Li <li.xin@linaro.org>
@@ -19,9 +20,19 @@
struct platform_device;
struct hisi_clocks;
+/*
+ * (Virtual) fixed clocks, often depended by crucial peripherals, require
+ * early initialization before device probing, thus cannot use devm APIs.
+ * Otherwise, kernel will defer those peripherals, causing boot failure.
+ *
+ * fixed_rate and fixed_factor clocks are driver-managed. They are freed by
+ * `hisi_clk_free` altogether.
+ *
+ * Other clocks are devm-managed.
+ */
struct hisi_clock_data {
- struct clk_onecell_data clk_data;
- void __iomem *base;
+ struct clk_hw_onecell_data *clk_data;
+ void __iomem *base;
const struct hisi_clocks *clks;
};
@@ -137,37 +148,46 @@ struct hisi_clocks {
int num, struct hisi_clock_data *data);
};
-struct clk *hisi_register_clkgate_sep(struct device *, const char *,
- const char *, unsigned long,
- void __iomem *, u8,
- u8, spinlock_t *);
-struct clk *hi6220_register_clkdiv(struct device *dev, const char *name,
- const char *parent_name, unsigned long flags, void __iomem *reg,
- u8 shift, u8 width, u32 mask_bit, spinlock_t *lock);
-
-struct hisi_clock_data *hisi_clk_alloc(struct platform_device *, int);
-struct hisi_clock_data *hisi_clk_init(struct device_node *, int);
-void hisi_clk_free(struct device_node *np, struct hisi_clock_data *data);
-int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *,
- int, struct hisi_clock_data *);
-int hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *,
- int, struct hisi_clock_data *);
-int hisi_clk_register_mux(const struct hisi_mux_clock *, int,
- struct hisi_clock_data *);
-struct clk *clk_register_hisi_phase(struct device *dev,
- const struct hisi_phase_clock *clks,
+struct clk_hw *
+devm_clk_hw_register_hisi_phase(struct device *dev, const struct hisi_phase_clock *clks,
void __iomem *base, spinlock_t *lock);
+struct clk_hw *
+devm_clk_hw_register_hisi_gate_sep(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 bit_idx,
+ u8 clk_gate_flags, spinlock_t *lock);
+struct clk_hw *
+devm_clk_hw_register_hi6220_divider(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 shift,
+ u8 width, u32 mask_bit, spinlock_t *lock);
+
+struct hisi_clock_data *hisi_clk_init(struct device_node *np, int nr);
+void hisi_clk_free(struct device_node *np, struct hisi_clock_data *data);
+
+int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *clks,
+ int num, struct hisi_clock_data *data);
+int hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *clks,
+ int num, struct hisi_clock_data *data);
+
+int hisi_clk_register_mux(struct device *dev,
+ const struct hisi_mux_clock *clks, int num,
+ struct hisi_clock_data *data);
int hisi_clk_register_phase(struct device *dev,
- const struct hisi_phase_clock *clks,
- int nums, struct hisi_clock_data *data);
-int hisi_clk_register_divider(const struct hisi_divider_clock *,
- int, struct hisi_clock_data *);
-int hisi_clk_register_gate(const struct hisi_gate_clock *,
- int, struct hisi_clock_data *);
-void hisi_clk_register_gate_sep(const struct hisi_gate_clock *,
- int, struct hisi_clock_data *);
-void hi6220_clk_register_divider(const struct hi6220_divider_clock *,
- int, struct hisi_clock_data *);
+ const struct hisi_phase_clock *clks,
+ int num, struct hisi_clock_data *data);
+int hisi_clk_register_divider(struct device *dev,
+ const struct hisi_divider_clock *clks,
+ int num, struct hisi_clock_data *data);
+int hisi_clk_register_gate(struct device *dev,
+ const struct hisi_gate_clock *clks,
+ int num, struct hisi_clock_data *data);
+int hisi_clk_register_gate_sep(struct device *dev,
+ const struct hisi_gate_clock *clks,
+ int num, struct hisi_clock_data *data);
+int hi6220_clk_register_divider(struct device *dev,
+ const struct hi6220_divider_clock *clks,
+ int num, struct hisi_clock_data *data);
int hisi_clk_register(struct device *dev, const struct hisi_clocks *clks,
struct hisi_clock_data *data);
@@ -180,22 +200,17 @@ int hisi_clk_remove(struct platform_device *pdev);
#define hisi_clk_unregister_fn(type) \
static inline \
-void hisi_clk_unregister_##type(const struct hisi_##type##_clock *clks, \
- int nums, struct hisi_clock_data *data) \
+void hisi_clk_unregister_##type(struct hisi_clock_data *data) \
{ \
- struct clk **clocks = data->clk_data.clks; \
int i; \
- for (i = 0; i < nums; i++) { \
- int id = clks[i].id; \
- if (clocks[id]) \
- clk_unregister_##type(clocks[id]); \
+ for (i = 0; i < data->clks->type##_clks_num; i++) { \
+ struct clk_hw *clk = data->clk_data->hws[data->clks->type##_clks[i].id]; \
+ if (clk && !IS_ERR(clk)) \
+ clk_hw_unregister_##type(clk); \
} \
}
hisi_clk_unregister_fn(fixed_rate)
hisi_clk_unregister_fn(fixed_factor)
-hisi_clk_unregister_fn(mux)
-hisi_clk_unregister_fn(divider)
-hisi_clk_unregister_fn(gate)
#endif /* __HISI_CLK_H */
diff --git a/drivers/clk/hisilicon/clkdivider-hi6220.c b/drivers/clk/hisilicon/clkdivider-hi6220.c
index 5348bafe694f..3c03b3e5b841 100644
--- a/drivers/clk/hisilicon/clkdivider-hi6220.c
+++ b/drivers/clk/hisilicon/clkdivider-hi6220.c
@@ -9,7 +9,7 @@
#include <linux/kernel.h>
#include <linux/clk-provider.h>
-#include <linux/slab.h>
+#include <linux/device.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/spinlock.h>
@@ -97,19 +97,19 @@ static const struct clk_ops hi6220_clkdiv_ops = {
.set_rate = hi6220_clkdiv_set_rate,
};
-struct clk *hi6220_register_clkdiv(struct device *dev, const char *name,
+struct clk_hw *devm_clk_hw_register_hi6220_divider(struct device *dev, const char *name,
const char *parent_name, unsigned long flags, void __iomem *reg,
u8 shift, u8 width, u32 mask_bit, spinlock_t *lock)
{
struct hi6220_clk_divider *div;
- struct clk *clk;
struct clk_init_data init;
struct clk_div_table *table;
u32 max_div, min_div;
int i;
+ int ret;
/* allocate the divider */
- div = kzalloc(sizeof(*div), GFP_KERNEL);
+ div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
if (!div)
return ERR_PTR(-ENOMEM);
@@ -117,11 +117,9 @@ struct clk *hi6220_register_clkdiv(struct device *dev, const char *name,
max_div = div_mask(width) + 1;
min_div = 1;
- table = kcalloc(max_div + 1, sizeof(*table), GFP_KERNEL);
- if (!table) {
- kfree(div);
+ table = devm_kcalloc(dev, max_div + 1, sizeof(*table), GFP_KERNEL);
+ if (!table)
return ERR_PTR(-ENOMEM);
- }
for (i = 0; i < max_div; i++) {
table[i].div = min_div + i;
@@ -144,11 +142,9 @@ struct clk *hi6220_register_clkdiv(struct device *dev, const char *name,
div->table = table;
/* register the clock */
- clk = clk_register(dev, &div->hw);
- if (IS_ERR(clk)) {
- kfree(table);
- kfree(div);
- }
+ ret = devm_clk_hw_register(dev, &div->hw);
+ if (ret)
+ return ERR_PTR(ret);
- return clk;
+ return &div->hw;
}
diff --git a/drivers/clk/hisilicon/clkgate-separated.c b/drivers/clk/hisilicon/clkgate-separated.c
index 90d858522967..dc64a8a0ab58 100644
--- a/drivers/clk/hisilicon/clkgate-separated.c
+++ b/drivers/clk/hisilicon/clkgate-separated.c
@@ -11,8 +11,8 @@
#include <linux/kernel.h>
#include <linux/clk-provider.h>
+#include <linux/device.h>
#include <linux/io.h>
-#include <linux/slab.h>
#include "clk.h"
@@ -80,17 +80,18 @@ static const struct clk_ops clkgate_separated_ops = {
.is_enabled = clkgate_separated_is_enabled,
};
-struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name,
- const char *parent_name,
- unsigned long flags,
- void __iomem *reg, u8 bit_idx,
- u8 clk_gate_flags, spinlock_t *lock)
+struct clk_hw *
+devm_clk_hw_register_hisi_gate_sep(struct device *dev, const char *name,
+ const char *parent_name,
+ unsigned long flags,
+ void __iomem *reg, u8 bit_idx,
+ u8 clk_gate_flags, spinlock_t *lock)
{
struct clkgate_separated *sclk;
- struct clk *clk;
struct clk_init_data init;
+ int ret;
- sclk = kzalloc(sizeof(*sclk), GFP_KERNEL);
+ sclk = devm_kzalloc(dev, sizeof(*sclk), GFP_KERNEL);
if (!sclk)
return ERR_PTR(-ENOMEM);
@@ -106,8 +107,9 @@ struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name,
sclk->hw.init = &init;
sclk->lock = lock;
- clk = clk_register(dev, &sclk->hw);
- if (IS_ERR(clk))
- kfree(sclk);
- return clk;
+ ret = devm_clk_hw_register(dev, &sclk->hw);
+ if (ret)
+ return ERR_PTR(ret);
+
+ return &sclk->hw;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v2 0/4] clk: hisilicon: Migrate devm APIs
2023-03-29 7:50 [PATCH v2 0/4] clk: hisilicon: Migrate devm APIs David Yang
` (3 preceding siblings ...)
2023-03-29 7:50 ` [PATCH v2 4/4] clk: hisilicon: Migrate devm APIs David Yang
@ 2023-04-05 19:39 ` Stephen Boyd
4 siblings, 0 replies; 9+ messages in thread
From: Stephen Boyd @ 2023-04-05 19:39 UTC (permalink / raw)
To: David Yang, linux-clk; +Cc: David Yang, Michael Turquette, linux-kernel
Quoting David Yang (2023-03-29 00:50:49)
> Migrate devm APIs for HiSilicon clock drivers and remove redundant codes.
>
> This series is a partial improvement of [1]
>
Run checkpatch.pl
WARNING: Macros with flow control statements should be avoided
#591: FILE: drivers/clk/hisilicon/clk.c:146:
+#define hisi_clk_register_fn(fn, type, stmt) \
+int fn(struct device *dev, const struct type *clks, \
+ int num, struct hisi_clock_data *data) \
+{ \
+ void __iomem *base = data->base; \
+ int i; \
+\
+ for (i = 0; i < num; i++) { \
+ const struct type *p_clk = &clks[i]; \
+ struct clk_hw *clk = stmt; \
+\
+ if (IS_ERR(clk)) { \
+ pr_err("%s: failed to register clock %s\n", \
+ __func__, p_clk->name); \
+ return PTR_ERR(clk); \
+ } \
+\
+ if (p_clk->alias) \
+ clk_hw_register_clkdev(clk, p_clk->alias, NULL); \
+\
+ data->clk_data->hws[p_clk->id] = clk; \
+ } \
+\
+ return 0; \
+} \
+EXPORT_SYMBOL_GPL(fn);
WARNING: macros should not use a trailing semicolon
#591: FILE: drivers/clk/hisilicon/clk.c:146:
+#define hisi_clk_register_fn(fn, type, stmt) \
+int fn(struct device *dev, const struct type *clks, \
+ int num, struct hisi_clock_data *data) \
+{ \
+ void __iomem *base = data->base; \
+ int i; \
+\
+ for (i = 0; i < num; i++) { \
+ const struct type *p_clk = &clks[i]; \
+ struct clk_hw *clk = stmt; \
+\
+ if (IS_ERR(clk)) { \
+ pr_err("%s: failed to register clock %s\n", \
+ __func__, p_clk->name); \
+ return PTR_ERR(clk); \
+ } \
+\
+ if (p_clk->alias) \
+ clk_hw_register_clkdev(clk, p_clk->alias, NULL); \
+\
+ data->clk_data->hws[p_clk->id] = clk; \
+ } \
+\
+ return 0; \
+} \
+EXPORT_SYMBOL_GPL(fn);
total: 0 errors, 2 warnings, 1019 lines checked
in patch 'clk: hisilicon: Migrate devm APIs' (8d960cbef61a)
WARNING: Prefer "GPL" over "GPL v2" - see commit bf7fbeeae6db ("module: Cure the MODULE_LICENSE "GPL" vs. "GPL v2" bogosity")
#627: FILE: drivers/clk/hisilicon/clk-hi6220.c:291:
+MODULE_LICENSE("GPL v2");
WARNING: DT compatible string "hisilicon,hip04-clock" appears un-documented -- check ./Documentation/devicetree/bindings/
#661: FILE: drivers/clk/hisilicon/clk-hip04.c:33:
+ { .compatible = "hisilicon,hip04-clock",
WARNING: Prefer "GPL" over "GPL v2" - see commit bf7fbeeae6db ("module: Cure the MODULE_LICENSE "GPL" vs. "GPL v2" bogosity")
#842: FILE: drivers/clk/hisilicon/clk-hix5hd2.c:337:
+MODULE_LICENSE("GPL v2");
total: 0 errors, 3 warnings, 779 lines checked
in patch 'clk: hisilicon: Convert to platform driver' (2681347c2636)
WARNING: Prefer "GPL" over "GPL v2" - see commit bf7fbeeae6db ("module: Cure the MODULE_LICENSE "GPL" vs. "GPL v2" bogosity")
#1044: FILE: drivers/clk/hisilicon/clk-hi3670.c:935:
+MODULE_LICENSE("GPL v2");
total: 0 errors, 1 warnings, 1481 lines checked
^ permalink raw reply [flat|nested] 9+ messages in thread