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From: Ryan Roberts <ryan.roberts@arm.com>
To: Jason Gunthorpe <jgg@ziepe.ca>
Cc: "Catalin Marinas" <catalin.marinas@arm.com>,
	"Mikołaj Lenczewski" <miko.lenczewski@arm.com>,
	yang@os.amperecomputing.com, will@kernel.org,
	jean-philippe@linaro.org, robin.murphy@arm.com, joro@8bytes.org,
	maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com,
	james.morse@arm.com, broonie@kernel.org, ardb@kernel.org,
	baohua@kernel.org, suzuki.poulose@arm.com, david@redhat.com,
	nicolinc@nvidia.com, jsnitsel@redhat.com, mshavit@google.com,
	kevin.tian@intel.com, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, iommu@lists.linux.dev
Subject: Re: [PATCH v7 4/4] arm64/mm: Elide tlbi in contpte_convert() under BBML2
Date: Wed, 25 Jun 2025 15:16:41 +0100	[thread overview]
Message-ID: <40c6e847-3be1-4d12-ab23-6ac5e0f1bd4a@arm.com> (raw)
In-Reply-To: <20250625133735.GB213144@ziepe.ca>

On 25/06/2025 14:37, Jason Gunthorpe wrote:
> On Wed, Jun 25, 2025 at 02:07:23PM +0100, Ryan Roberts wrote:
>> I think what you are saying is that despite going via invalid, the HW may see
>> this direct transition:
>>
>> +----+----+----+----+
>> |RO,n|RO,n|RO,n|RW,n|
>> +----+----+----+----+
>> to:
>> +----+----+----+----+
>> |RO,c|RO,c|RO,c|RO,c|
>> +----+----+----+----+
>>
>> There are 2 logical operations here. The first is changing the permissions of
>> the last entry. The second is changing the size of the entry.
>>
>> As I understand it, it's permissible in the architecture to update the
>> permissions of the a PTE without break-before-make and without issuing a tlbi
>> afterwards; in that case the HW may apply either the old permissions or the new
>> permissions up until a future tlbi (after which the new permissions are
>> guarranteed). That's the first logical operation.
>>
>> The second logical operation is permitted by FEAT_BBM level 2.
>>
>> So both logical operations are permitted and the Arm ARM doesn't mention any
>> requirement to "separate" these operations with a tlbi or anything else, as far
>> as I can see.
>>
>> So I would interpret that combining these 2 in the way we have should be safe.
>> RNGLXZ and RJQQTC give further insight into the spirit of the spec. But I agree
>> this isn't spelled out super clearly.
>>
>> Perhaps we can move forwards based on this understanding, and I will seek some
>> clarifying words to be added to the Arm ARM?
> 
> FWIW this matches my understanding as well.
> 
> AFAIK the actual physical issue for BBM < 2 is the TLB lookup HW
> cannot tolerate having two entries that overlap in address because of
> different sizes. Every lookup must return exactly one result. If more
> results are returned the HW fails in some way.
> 
> For BBM 2 if the HW lookup gets more than one result the HW selects
> one unpredictably and uses that.
> 
> Permissions shouldn't have any impact because they do not effect how
> the lookup is performed, they are the result of the lookup.

Totally agree with all of this! But ideally we want the Arm ARM to be
unambiguous so that we can implement against that rather than against our
understanding of the HW issues and what the Arm ARM "almost certainly intended".

> 
> I've been looking at implementing BBM 2 support on the iommu side and
> I didn't see anything that said we cannot do arbitary transformations
> under BBM 2? For instance when degrading from a contiguous range of
> block descriptors down to single page descriptors I'm expecting to go
> like:
>     16x2M -> 2M -> 4k -> FLUSH

If this is just changing sizes, it's definitely, explcitly safe in the Arm ARM
(I haven't read the equivalent SMMU text). And there isn't a requirement to
flush at the end. You only need to flush the (sub-)ranges where permissions or
whatever have changed.

> 
> Jason


      reply	other threads:[~2025-06-25 14:16 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-17  9:51 [PATCH v7 0/4] Initial BBML2 support for contpte_convert() Mikołaj Lenczewski
2025-06-17  9:51 ` [PATCH v7 1/4] arm64: cpufeature: Introduce MATCH_ALL_EARLY_CPUS capability type Mikołaj Lenczewski
2025-06-17 10:20   ` Suzuki K Poulose
2025-06-17  9:51 ` [PATCH v7 2/4] arm64: Add BBM Level 2 cpu feature Mikołaj Lenczewski
2025-06-17 10:35   ` Suzuki K Poulose
2025-06-18 14:07   ` Ryan Roberts
2025-06-19  8:57     ` Mikołaj Lenczewski
2025-06-19  9:20       ` Ryan Roberts
2025-06-19 11:51         ` Mikołaj Lenczewski
2025-06-19 11:05   ` Catalin Marinas
2025-06-19 11:51     ` Mikołaj Lenczewski
2025-06-19 13:46       ` Catalin Marinas
2025-06-19 14:46         ` Mikołaj Lenczewski
2025-06-17  9:51 ` [PATCH v7 3/4] iommu/arm: Add BBM Level 2 smmu feature Mikołaj Lenczewski
2025-06-19 11:36   ` Catalin Marinas
2025-06-17  9:51 ` [PATCH v7 4/4] arm64/mm: Elide tlbi in contpte_convert() under BBML2 Mikołaj Lenczewski
2025-06-19 19:29   ` Catalin Marinas
2025-06-19 19:47     ` Catalin Marinas
2025-06-20 16:10     ` Ryan Roberts
2025-06-25 13:07       ` Ryan Roberts
2025-06-25 13:37         ` Jason Gunthorpe
2025-06-25 14:16           ` Ryan Roberts [this message]

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