Re: [PATCH] Configure IDE probe delays

Jeff Garzik
2004-09-01T14:44:02Z

Mark Lord wrote:
> Bartlomiej Zolnierkiewicz wrote:
>
>>
>>> What determines whether 48 bit addressing will be used then?
>>
>>
>> Availability of 48-bit addressing feature set and host capabilities
>> (some don't support LBA48 when DMA is used etc.).
>
>
> I haven't examined the "released" IDE drivers in some time,
> but one optimisation that can save a LOT of CPU usage
> is for the driver to only use LBA48 *when necessary*,
> and use LBA28 I/O otherwise.
>
> Each access to an IDE register typically chews up 600+ns,
> or the equivalent of a couple thousand instruction executions
> on a modern core. Avoiding LBA48 when it's not needed will
> save four such accesses per I/O, or about 2.5us.

Doing this is either pointless or impossible on newer SATA controllers.
Most are memory-mapped I/O not PIO, where the high-order bits of the
ATA taskfile are accessed due to an extended register size, not
"double-pumping" a FIFO.

Even-newer SATA controllers are FIS-based rather than taskfile-based, so
you pass it a FIS (containing all the registers) unconditionally.

Jeff