[PATCH 0/3] clk: ralink: mtmips: some fixes and sdhc clock support

[PATCH 0/3] clk: ralink: mtmips: some fixes and sdhc clock support

[Sergio Paracuellos]

Hi Stephen,

The following first two patches contains several fixes for having a correct
clock plan from the beggining in old ralink SoCs that could not be tested
when the driver was mainlained due to the lack of users. Now some issues
have been reported regarding RT3883 in openWRT[0] so I am addressing and 
fixing them here.

The last patch adds new clocks to properly support sdhc 48 MHz clock for
Mt7620, Mt7628 and Mt7688 SoCs. OpenWRT people updated to use SDHC upstream
driver so they were forced to add a not desired fixed dts node[1] to make it
works. The correct thing to do is just support it in mtmips driver. Hence
we have add it here.

Thanks in advance for your time.

Best regards,
    Sergio Paracuellos

[0]: https://github.com/openwrt/openwrt/issues/16054
[1]: https://github.com/openwrt/openwrt/pull/15896/files

Sergio Paracuellos (3):
  clk: ralink: mtmips: fix clock plan for Ralink SoC RT3883
  clk: ralink: mtmips: fix clocks probe order in oldest ralink SoCs
  clk: ralink: mtmips: add mmc related clocks for SoCs MT7620, MT7628
    and MT7688

 drivers/clk/ralink/clk-mtmips.c | 56 ++++++++++++++++++++++++---------
 1 file changed, 41 insertions(+), 15 deletions(-)

-- 
2.25.1

[PATCH 1/3] clk: ralink: mtmips: fix clock plan for Ralink SoC RT3883

[Sergio Paracuellos]

Clock plan for Ralink SoC RT3883 needs an extra 'periph' clock to properly
set some peripherals that has this clock as their parent. When this driver
was mainlined we could not find any active users of this SoC so we cannot
perform any real tests for it. Now, one user of a Belkin f9k1109 version 1
device which uses this SoC appear and reported some issues in openWRT:
- https://github.com/openwrt/openwrt/issues/16054
The peripherals that are wrong are 'uart', 'i2c', 'i2s' and 'uartlite' which
has a not defined 'periph' clock as parent. Hence, introduce it to have a
properly working clock plan for this SoC.

Fixes: 6f3b15586eef ("clk: ralink: add clock and reset driver for MTMIPS SoCs")
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/clk/ralink/clk-mtmips.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/ralink/clk-mtmips.c b/drivers/clk/ralink/clk-mtmips.c
index 50a443bf79ec..62f9801ecd3a 100644
--- a/drivers/clk/ralink/clk-mtmips.c
+++ b/drivers/clk/ralink/clk-mtmips.c
@@ -267,6 +267,11 @@ static struct mtmips_clk_fixed rt305x_fixed_clocks[] = {
 	CLK_FIXED("xtal", NULL, 40000000)
 };
 
+static struct mtmips_clk_fixed rt3883_fixed_clocks[] = {
+	CLK_FIXED("xtal", NULL, 40000000),
+	CLK_FIXED("periph", "xtal", 40000000)
+};
+
 static struct mtmips_clk_fixed rt3352_fixed_clocks[] = {
 	CLK_FIXED("periph", "xtal", 40000000)
 };
@@ -779,8 +784,8 @@ static const struct mtmips_clk_data rt3352_clk_data = {
 static const struct mtmips_clk_data rt3883_clk_data = {
 	.clk_base = rt3883_clks_base,
 	.num_clk_base = ARRAY_SIZE(rt3883_clks_base),
-	.clk_fixed = rt305x_fixed_clocks,
-	.num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
+	.clk_fixed = rt3883_fixed_clocks,
+	.num_clk_fixed = ARRAY_SIZE(rt3883_fixed_clocks),
 	.clk_factor = NULL,
 	.num_clk_factor = 0,
 	.clk_periph = rt5350_pherip_clks,
-- 
2.25.1

[PATCH 2/3] clk: ralink: mtmips: fix clocks probe order in oldest ralink SoCs

[Sergio Paracuellos]

Base clocks are the first in being probed and are real dependencies of the
rest of fixed, factor and peripheral clocks. For old ralink SoCs RT2880,
RT305x and RT3883 'xtal' must be defined first since in any other case,
when fixed clocks are probed they are delayed until 'xtal' is probed so the
following warning appears:

 WARNING: CPU: 0 PID: 0 at drivers/clk/ralink/clk-mtmips.c:499 rt3883_bus_recalc_rate+0x98/0x138
 Modules linked in:
 CPU: 0 PID: 0 Comm: swapper Not tainted 6.6.43 #0
 Stack : 805e58d0 00000000 00000004 8004f950 00000000 00000004 00000000 00000000
 80669c54 80830000 80700000 805ae570 80670068 00000001 80669bf8 00000000
 00000000 00000000 805ae570 80669b38 00000020 804db7dc 00000000 00000000
 203a6d6d 80669b78 80669e48 70617773 00000000 805ae570 00000000 00000009
 00000000 00000001 00000004 00000001 00000000 00000000 83fe43b0 00000000
 ...
 Call Trace:
 [<800065d0>] show_stack+0x64/0xf4
 [<804bca14>] dump_stack_lvl+0x38/0x60
 [<800218ac>] __warn+0x94/0xe4
 [<8002195c>] warn_slowpath_fmt+0x60/0x94
 [<80259ff8>] rt3883_bus_recalc_rate+0x98/0x138
 [<80254530>] __clk_register+0x568/0x688
 [<80254838>] of_clk_hw_register+0x18/0x2c
 [<8070b910>] rt2880_clk_of_clk_init_driver+0x18c/0x594
 [<8070b628>] of_clk_init+0x1c0/0x23c
 [<806fc448>] plat_time_init+0x58/0x18c
 [<806fdaf0>] time_init+0x10/0x6c
 [<806f9bc4>] start_kernel+0x458/0x67c

 ---[ end trace 0000000000000000 ]---

When this driver was mainlined we could not find any active users of old
ralink SoCs so we cannot perform any real tests for them. Now, one user
of a Belkin f9k1109 version 1 device which uses RT3883 SoC appeared and
reported some issues in openWRT:
- https://github.com/openwrt/openwrt/issues/16054

Thus, define a 'rt2880_xtal_recalc_rate()' just returning the expected
frequency 40Mhz and use it along the old ralink SoCs to have a correct
boot trace with no warnings and a working clock plan from the beggining.

Fixes: 6f3b15586eef ("clk: ralink: add clock and reset driver for MTMIPS SoCs")
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/clk/ralink/clk-mtmips.c | 21 +++++++++++++--------
 1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/ralink/clk-mtmips.c b/drivers/clk/ralink/clk-mtmips.c
index 62f9801ecd3a..76285fbbdeaa 100644
--- a/drivers/clk/ralink/clk-mtmips.c
+++ b/drivers/clk/ralink/clk-mtmips.c
@@ -263,10 +263,6 @@ static int mtmips_register_pherip_clocks(struct device_node *np,
 		.rate = _rate		 \
 	}
 
-static struct mtmips_clk_fixed rt305x_fixed_clocks[] = {
-	CLK_FIXED("xtal", NULL, 40000000)
-};
-
 static struct mtmips_clk_fixed rt3883_fixed_clocks[] = {
 	CLK_FIXED("xtal", NULL, 40000000),
 	CLK_FIXED("periph", "xtal", 40000000)
@@ -371,6 +367,12 @@ static inline struct mtmips_clk *to_mtmips_clk(struct clk_hw *hw)
 	return container_of(hw, struct mtmips_clk, hw);
 }
 
+static unsigned long rt2880_xtal_recalc_rate(struct clk_hw *hw,
+					     unsigned long parent_rate)
+{
+	return 40000000;
+}
+
 static unsigned long rt5350_xtal_recalc_rate(struct clk_hw *hw,
 					     unsigned long parent_rate)
 {
@@ -682,10 +684,12 @@ static unsigned long mt76x8_cpu_recalc_rate(struct clk_hw *hw,
 }
 
 static struct mtmips_clk rt2880_clks_base[] = {
+	{ CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) },
 	{ CLK_BASE("cpu", "xtal", rt2880_cpu_recalc_rate) }
 };
 
 static struct mtmips_clk rt305x_clks_base[] = {
+	{ CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) },
 	{ CLK_BASE("cpu", "xtal", rt305x_cpu_recalc_rate) }
 };
 
@@ -695,6 +699,7 @@ static struct mtmips_clk rt3352_clks_base[] = {
 };
 
 static struct mtmips_clk rt3883_clks_base[] = {
+	{ CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) },
 	{ CLK_BASE("cpu", "xtal", rt3883_cpu_recalc_rate) },
 	{ CLK_BASE("bus", "cpu", rt3883_bus_recalc_rate) }
 };
@@ -751,8 +756,8 @@ static int mtmips_register_clocks(struct device_node *np,
 static const struct mtmips_clk_data rt2880_clk_data = {
 	.clk_base = rt2880_clks_base,
 	.num_clk_base = ARRAY_SIZE(rt2880_clks_base),
-	.clk_fixed = rt305x_fixed_clocks,
-	.num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
+	.clk_fixed = NULL,
+	.num_clk_fixed = 0,
 	.clk_factor = rt2880_factor_clocks,
 	.num_clk_factor = ARRAY_SIZE(rt2880_factor_clocks),
 	.clk_periph = rt2880_pherip_clks,
@@ -762,8 +767,8 @@ static const struct mtmips_clk_data rt2880_clk_data = {
 static const struct mtmips_clk_data rt305x_clk_data = {
 	.clk_base = rt305x_clks_base,
 	.num_clk_base = ARRAY_SIZE(rt305x_clks_base),
-	.clk_fixed = rt305x_fixed_clocks,
-	.num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
+	.clk_fixed = NULL,
+	.num_clk_fixed = 0,
 	.clk_factor = rt305x_factor_clocks,
 	.num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
 	.clk_periph = rt305x_pherip_clks,
-- 
2.25.1

[PATCH 3/3] clk: ralink: mtmips: add mmc related clocks for SoCs MT7620, MT7628 and MT7688

[Sergio Paracuellos]

Original architecture clock code from where this driver was derived did not
include nothing related to mmc clocks. OpenWRT people started to use mtk-sd
upstream driver recently and they were forced to use a dts 'fixed-clock'
node with 48 MHz clock:
- https://github.com/openwrt/openwrt/pull/15896
The proper thing to do to avoid that is to add the mmc related clocks to the
driver to avoid a dts with fixed clocks nodes. The minimal documentation in
the mt7620 programming guide says that there is a BBP_PLL clock of 480 MHz
derived from the 40 MHz XTAL and from there a clock divider by ten produces
the desired SDHC clock of 48 MHz for the mmc. Hence add a fixed clock 'bbppll'
and factor clock 'sdhc' ten divider child to properly set the 'mmc' peripheral
clock with the desired 48 Mhz rate.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/clk/ralink/clk-mtmips.c | 30 +++++++++++++++++++++++-------
 1 file changed, 23 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/ralink/clk-mtmips.c b/drivers/clk/ralink/clk-mtmips.c
index 76285fbbdeaa..97b8ca0f9181 100644
--- a/drivers/clk/ralink/clk-mtmips.c
+++ b/drivers/clk/ralink/clk-mtmips.c
@@ -207,6 +207,7 @@ static struct mtmips_clk mt7620_pherip_clks[] = {
 	{ CLK_PERIPH("10000b00.spi", "bus") },
 	{ CLK_PERIPH("10000b40.spi", "bus") },
 	{ CLK_PERIPH("10000c00.uartlite", "periph") },
+	{ CLK_PERIPH("10130000.mmc", "sdhc") },
 	{ CLK_PERIPH("10180000.wmac", "xtal") }
 };
 
@@ -220,6 +221,7 @@ static struct mtmips_clk mt76x8_pherip_clks[] = {
 	{ CLK_PERIPH("10000c00.uart0", "periph") },
 	{ CLK_PERIPH("10000d00.uart1", "periph") },
 	{ CLK_PERIPH("10000e00.uart2", "periph") },
+	{ CLK_PERIPH("10130000.mmc", "sdhc") },
 	{ CLK_PERIPH("10300000.wmac", "xtal") }
 };
 
@@ -272,8 +274,13 @@ static struct mtmips_clk_fixed rt3352_fixed_clocks[] = {
 	CLK_FIXED("periph", "xtal", 40000000)
 };
 
+static struct mtmips_clk_fixed mt7620_fixed_clocks[] = {
+	CLK_FIXED("bbppll", "xtal", 480000000)
+};
+
 static struct mtmips_clk_fixed mt76x8_fixed_clocks[] = {
-	CLK_FIXED("pcmi2s", "xtal", 480000000),
+	CLK_FIXED("bbppll", "xtal", 480000000),
+	CLK_FIXED("pcmi2s", "bbppll", 480000000),
 	CLK_FIXED("periph", "xtal", 40000000)
 };
 
@@ -328,6 +335,15 @@ static struct mtmips_clk_factor rt305x_factor_clocks[] = {
 	CLK_FACTOR("bus", "cpu", 1, 3)
 };
 
+static struct mtmips_clk_factor mt7620_factor_clocks[] = {
+	CLK_FACTOR("sdhc", "bbppll", 1, 10)
+};
+
+static struct mtmips_clk_factor mt76x8_factor_clocks[] = {
+	CLK_FACTOR("bus", "cpu", 1, 3),
+	CLK_FACTOR("sdhc", "bbppll", 1, 10)
+};
+
 static int mtmips_register_factor_clocks(struct clk_hw_onecell_data *clk_data,
 					 struct mtmips_clk_priv *priv)
 {
@@ -811,10 +827,10 @@ static const struct mtmips_clk_data rt5350_clk_data = {
 static const struct mtmips_clk_data mt7620_clk_data = {
 	.clk_base = mt7620_clks_base,
 	.num_clk_base = ARRAY_SIZE(mt7620_clks_base),
-	.clk_fixed = NULL,
-	.num_clk_fixed = 0,
-	.clk_factor = NULL,
-	.num_clk_factor = 0,
+	.clk_fixed = mt7620_fixed_clocks,
+	.num_clk_fixed = ARRAY_SIZE(mt7620_fixed_clocks),
+	.clk_factor = mt7620_factor_clocks,
+	.num_clk_factor = ARRAY_SIZE(mt7620_factor_clocks),
 	.clk_periph = mt7620_pherip_clks,
 	.num_clk_periph = ARRAY_SIZE(mt7620_pherip_clks),
 };
@@ -824,8 +840,8 @@ static const struct mtmips_clk_data mt76x8_clk_data = {
 	.num_clk_base = ARRAY_SIZE(mt76x8_clks_base),
 	.clk_fixed = mt76x8_fixed_clocks,
 	.num_clk_fixed = ARRAY_SIZE(mt76x8_fixed_clocks),
-	.clk_factor = rt305x_factor_clocks,
-	.num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
+	.clk_factor = mt76x8_factor_clocks,
+	.num_clk_factor = ARRAY_SIZE(mt76x8_factor_clocks),
 	.clk_periph = mt76x8_pherip_clks,
 	.num_clk_periph = ARRAY_SIZE(mt76x8_pherip_clks),
 };
-- 
2.25.1

Re: [PATCH 0/3] clk: ralink: mtmips: some fixes and sdhc clock support

[Sergio Paracuellos]

On Tue, Sep 10, 2024 at 6:40 AM Sergio Paracuellos
<sergio.paracuellos@gmail.com> wrote:
>
> Hi Stephen,
>
> The following first two patches contains several fixes for having a correct
> clock plan from the beggining in old ralink SoCs that could not be tested
> when the driver was mainlained due to the lack of users. Now some issues
> have been reported regarding RT3883 in openWRT[0] so I am addressing and
> fixing them here.
>
> The last patch adds new clocks to properly support sdhc 48 MHz clock for
> Mt7620, Mt7628 and Mt7688 SoCs. OpenWRT people updated to use SDHC upstream
> driver so they were forced to add a not desired fixed dts node[1] to make it
> works. The correct thing to do is just support it in mtmips driver. Hence
> we have add it here.
>
> Thanks in advance for your time.
>
> Best regards,
>     Sergio Paracuellos
>
> [0]: https://github.com/openwrt/openwrt/issues/16054
> [1]: https://github.com/openwrt/openwrt/pull/15896/files
>
> Sergio Paracuellos (3):
>   clk: ralink: mtmips: fix clock plan for Ralink SoC RT3883
>   clk: ralink: mtmips: fix clocks probe order in oldest ralink SoCs
>   clk: ralink: mtmips: add mmc related clocks for SoCs MT7620, MT7628
>     and MT7688
>
>  drivers/clk/ralink/clk-mtmips.c | 56 ++++++++++++++++++++++++---------
>  1 file changed, 41 insertions(+), 15 deletions(-)

Gentle ping on this series :-)

Thanks,
    Sergio Paracuelllos
>
> --
> 2.25.1
>

Re: [PATCH 0/3] clk: ralink: mtmips: some fixes and sdhc clock support

[Sergio Paracuellos]

On Thu, Oct 17, 2024 at 8:41 AM Sergio Paracuellos
<sergio.paracuellos@gmail.com> wrote:
>
> On Tue, Sep 10, 2024 at 6:40 AM Sergio Paracuellos
> <sergio.paracuellos@gmail.com> wrote:
> >
> > Hi Stephen,
> >
> > The following first two patches contains several fixes for having a correct
> > clock plan from the beggining in old ralink SoCs that could not be tested
> > when the driver was mainlained due to the lack of users. Now some issues
> > have been reported regarding RT3883 in openWRT[0] so I am addressing and
> > fixing them here.
> >
> > The last patch adds new clocks to properly support sdhc 48 MHz clock for
> > Mt7620, Mt7628 and Mt7688 SoCs. OpenWRT people updated to use SDHC upstream
> > driver so they were forced to add a not desired fixed dts node[1] to make it
> > works. The correct thing to do is just support it in mtmips driver. Hence
> > we have add it here.
> >
> > Thanks in advance for your time.
> >
> > Best regards,
> >     Sergio Paracuellos
> >
> > [0]: https://github.com/openwrt/openwrt/issues/16054
> > [1]: https://github.com/openwrt/openwrt/pull/15896/files
> >
> > Sergio Paracuellos (3):
> >   clk: ralink: mtmips: fix clock plan for Ralink SoC RT3883
> >   clk: ralink: mtmips: fix clocks probe order in oldest ralink SoCs
> >   clk: ralink: mtmips: add mmc related clocks for SoCs MT7620, MT7628
> >     and MT7688
> >
> >  drivers/clk/ralink/clk-mtmips.c | 56 ++++++++++++++++++++++++---------
> >  1 file changed, 41 insertions(+), 15 deletions(-)
>
> Gentle ping on this series :-)

Another gentle ping on this series :-)

Thanks in advance for your time.

Best regards,
     Sergio Paracuellos

Re: [PATCH 1/3] clk: ralink: mtmips: fix clock plan for Ralink SoC RT3883

[Stephen Boyd]

Quoting Sergio Paracuellos (2024-09-09 21:40:22)
> Clock plan for Ralink SoC RT3883 needs an extra 'periph' clock to properly
> set some peripherals that has this clock as their parent. When this driver
> was mainlined we could not find any active users of this SoC so we cannot
> perform any real tests for it. Now, one user of a Belkin f9k1109 version 1
> device which uses this SoC appear and reported some issues in openWRT:
> - https://github.com/openwrt/openwrt/issues/16054
> The peripherals that are wrong are 'uart', 'i2c', 'i2s' and 'uartlite' which
> has a not defined 'periph' clock as parent. Hence, introduce it to have a
> properly working clock plan for this SoC.
> 
> Fixes: 6f3b15586eef ("clk: ralink: add clock and reset driver for MTMIPS SoCs")
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> ---

Applied to clk-next

Re: [PATCH 2/3] clk: ralink: mtmips: fix clocks probe order in oldest ralink SoCs

[Stephen Boyd]

Quoting Sergio Paracuellos (2024-09-09 21:40:23)
> Base clocks are the first in being probed and are real dependencies of the
> rest of fixed, factor and peripheral clocks. For old ralink SoCs RT2880,
> RT305x and RT3883 'xtal' must be defined first since in any other case,
> when fixed clocks are probed they are delayed until 'xtal' is probed so the
> following warning appears:
> 
>  WARNING: CPU: 0 PID: 0 at drivers/clk/ralink/clk-mtmips.c:499 rt3883_bus_recalc_rate+0x98/0x138
>  Modules linked in:
>  CPU: 0 PID: 0 Comm: swapper Not tainted 6.6.43 #0
>  Stack : 805e58d0 00000000 00000004 8004f950 00000000 00000004 00000000 00000000
>  80669c54 80830000 80700000 805ae570 80670068 00000001 80669bf8 00000000
>  00000000 00000000 805ae570 80669b38 00000020 804db7dc 00000000 00000000
>  203a6d6d 80669b78 80669e48 70617773 00000000 805ae570 00000000 00000009
>  00000000 00000001 00000004 00000001 00000000 00000000 83fe43b0 00000000
>  ...
>  Call Trace:
>  [<800065d0>] show_stack+0x64/0xf4
>  [<804bca14>] dump_stack_lvl+0x38/0x60
>  [<800218ac>] __warn+0x94/0xe4
>  [<8002195c>] warn_slowpath_fmt+0x60/0x94
>  [<80259ff8>] rt3883_bus_recalc_rate+0x98/0x138
>  [<80254530>] __clk_register+0x568/0x688
>  [<80254838>] of_clk_hw_register+0x18/0x2c
>  [<8070b910>] rt2880_clk_of_clk_init_driver+0x18c/0x594
>  [<8070b628>] of_clk_init+0x1c0/0x23c
>  [<806fc448>] plat_time_init+0x58/0x18c
>  [<806fdaf0>] time_init+0x10/0x6c
>  [<806f9bc4>] start_kernel+0x458/0x67c
> 
>  ---[ end trace 0000000000000000 ]---

Applied to clk-next

Re: [PATCH 3/3] clk: ralink: mtmips: add mmc related clocks for SoCs MT7620, MT7628 and MT7688

[Stephen Boyd]

Quoting Sergio Paracuellos (2024-09-09 21:40:24)
> Original architecture clock code from where this driver was derived did not
> include nothing related to mmc clocks. OpenWRT people started to use mtk-sd
> upstream driver recently and they were forced to use a dts 'fixed-clock'
> node with 48 MHz clock:
> - https://github.com/openwrt/openwrt/pull/15896
> The proper thing to do to avoid that is to add the mmc related clocks to the
> driver to avoid a dts with fixed clocks nodes. The minimal documentation in
> the mt7620 programming guide says that there is a BBP_PLL clock of 480 MHz
> derived from the 40 MHz XTAL and from there a clock divider by ten produces
> the desired SDHC clock of 48 MHz for the mmc. Hence add a fixed clock 'bbppll'
> and factor clock 'sdhc' ten divider child to properly set the 'mmc' peripheral
> clock with the desired 48 Mhz rate.
> 
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> ---

Applied to clk-next