From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85F87C433EF for ; Wed, 13 Oct 2021 10:59:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6ED68610E5 for ; Wed, 13 Oct 2021 10:59:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233690AbhJMLBU convert rfc822-to-8bit (ORCPT ); Wed, 13 Oct 2021 07:01:20 -0400 Received: from gloria.sntech.de ([185.11.138.130]:44306 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233785AbhJMLAv (ORCPT ); Wed, 13 Oct 2021 07:00:51 -0400 Received: from ip5f5a6e92.dynamic.kabel-deutschland.de ([95.90.110.146] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1maby7-0004L8-Os; Wed, 13 Oct 2021 12:58:43 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Anup Patel Cc: Guo Ren , Atish Patra , Marc Zyngier , Thomas Gleixner , Palmer Dabbelt , "linux-kernel@vger.kernel.org List" , linux-riscv , Guo Ren , Rob Herring , Palmer Dabbelt Subject: Re: [PATCH V3 1/2] dt-bindings: update riscv plic compatible string Date: Wed, 13 Oct 2021 12:58:42 +0200 Message-ID: <4123505.Qt7VF8zqPO@diego> In-Reply-To: References: <20211013012149.2834212-1-guoren@kernel.org> <4027415.QZv1u5a1DM@diego> MIME-Version: 1.0 Content-Transfer-Encoding: 8BIT Content-Type: text/plain; charset="iso-8859-1" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am Mittwoch, 13. Oktober 2021, 11:49:20 CEST schrieb Anup Patel: > On Wed, Oct 13, 2021 at 3:13 PM Heiko Stübner wrote: > > > > Am Mittwoch, 13. Oktober 2021, 11:19:53 CEST schrieb Anup Patel: > > > On Wed, Oct 13, 2021 at 2:44 PM Heiko Stübner wrote: > > > > > > > > Am Mittwoch, 13. Oktober 2021, 11:11:26 CEST schrieb Anup Patel: > > > > > On Wed, Oct 13, 2021 at 2:27 PM Heiko Stübner wrote: > > > > > > > > > > > > Hi Anup, > > > > > > > > > > > > Am Mittwoch, 13. Oktober 2021, 07:11:46 CEST schrieb Anup Patel: > > > > > > > On Wed, Oct 13, 2021 at 6:52 AM wrote: > > > > > > > > > > > > > > > > From: Guo Ren > > > > > > > > > > > > > > > > Add the compatible string "thead,c900-plic" to the riscv plic > > > > > > > > bindings to support SOCs with thead,c9xx processor cores. > > > > > > > > > > > > > > > > Signed-off-by: Guo Ren > > > > > > > > Cc: Rob Herring > > > > > > > > Cc: Palmer Dabbelt > > > > > > > > Cc: Anup Patel > > > > > > > > Cc: Atish Patra > > > > > > > > > > > > > > > > --- > > > > > > > > > > > > > > > > Changes since V3: > > > > > > > > - Rename "c9xx" to "c900" > > > > > > > > - Add thead,c900-plic in the description section > > > > > > > > --- > > > > > > > > .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 6 ++++++ > > > > > > > > 1 file changed, 6 insertions(+) > > > > > > > > > > > > > > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > > > > > > > > index 08d5a57ce00f..82629832e5a5 100644 > > > > > > > > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > > > > > > > > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > > > > > > > > @@ -35,6 +35,11 @@ description: > > > > > > > > contains a specific memory layout, which is documented in chapter 8 of the > > > > > > > > SiFive U5 Coreplex Series Manual . > > > > > > > > > > > > > > > > + While the "thead,c900-plic" would mask IRQ with readl(claim), so it needn't > > > > > > > > + mask/unmask which needed in RISC-V PLIC. When in IRQS_ONESHOT & IRQCHIP_EOI_THREADED > > > > > > > > + path, unnecessary mask operation would cause a blocking irq bug in thead,c900-plic. > > > > > > > > + Because when IRQ is disabled in c900, writel(hwirq, claim) would be invalid. > > > > > > > > > > > > > > This is a totally incorrect description of the errata required for C9xx PLIC. > > > > > > > > > > > > > > Please don't project non-compliance as a feature of C9xx PLIC. > > > > > > > > > > > > > > > + > > > > > > > > maintainers: > > > > > > > > - Sagar Kadam > > > > > > > > - Paul Walmsley > > > > > > > > @@ -46,6 +51,7 @@ properties: > > > > > > > > - enum: > > > > > > > > - sifive,fu540-c000-plic > > > > > > > > - canaan,k210-plic > > > > > > > > + - thead,c900-plic > > > > > > > > > > > > we still want specific SoC names in the compatible, the "c900" > > > > > > is still a sort-of placeholder. > > > > > > > > > > Yes, we need "c900" compatible string as well. The "c9xx" > > > > > compatible string is for the custom PLIC spec followed by T-HEAD. > > > > > > > > What I meant was that the soc-specific string should name the > > > > actual SoC (c906, c910) and not some imaginary chip ;-) > > > > > > Ahh, yes. It should be an actual soc name in the compatible > > > string. > > > > > > For example, SiFive uses "fu540" string to identify some of the > > > devices on both SiFive unleashed and SiFive unmatched boards. > > > > > > I was under the impression that "c900" is an actual SoC name. > > > > > > Regards, > > > Anup > > > > > > > > > > > See for example mali gpu bindings for a similar reference > > > > in devicetree/bindings/gpu/arm,mali-bifrost.yaml . > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > - const: sifive,plic-1.0.0 > > > > > > > > > > > > > > The PLIC DT node requires two compatible string: > > > > > > > , > > > > > > > > > > > > > > The C9xx PLIC is not RISC-V PLIC so, the DT node should > > > > > > > be: "thead,c900-plic", "thead,c9xx-plic" > > > > > > > > > > > > > > You need to change "- const: sifive,plic-1.0.0" to > > > > > > > - enum: > > > > > > > - sifive,plic-1.0.0 > > > > > > > - thead,c9xx-plic > > > > isn't XuanTie the series containing the c906 and c910? > > So maybe > > thead,xuantie-plic > > for the spec compatible. > > > > So doing in full > > compatible = "thead,c906-plic", "thead,xuantie-plic" > > This is a much better suggestion. I will let Guo decide. In any case, we'll also need a new entry in devicetree/bindings/vendor-prefixes.yaml for the "thead" prefix in a separate patch, as it looks like such a thing is also still missing. Heiko