Re: [PATCH 1/8] phy: qcom-qmp: pcs-pcie: Add v6.30 register offsets

Krzysztof Kozlowski
2024-08-27T11:37:12Z

On Mon, Aug 26, 2024 at 11:36:24PM -0700, Qiang Yu wrote:
> x1e80100 SoC uses QMP phy with version v6.30 for PCIe Gen4 x8. Add the new
> PCS PCIE specific offsets in a dedicated header file.
>
> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
> ---
> .../qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h | 25 +++++++++++++++++++
> 1 file changed, 25 insertions(+)
> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h
> new file mode 100644
> index 000000000000..5a58ff197e6e
> --- /dev/null
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h
> @@ -0,0 +1,25 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2024 Qualcomm Innovation Center. All rights reserved.
> + */
> +
> +#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_30_H_
> +#define QCOM_PHY_QMP_PCS_PCIE_V6_30_H_
> +
> +/* Only for QMP V6_30 PHY - PCIE have different offsets than V6 */
> +#define QPHY_PCIE_V6_30_PCS_POWER_STATE_CONFIG2 0x014
> +#define QPHY_PCIE_V6_30_PCS_TX_RX_CONFIG 0x020
> +#define QPHY_PCIE_V6_30_PCS_ENDPOINT_REFCLK_DRIVE 0x024
> +#define QPHY_PCIE_V6_30_PCS_OSC_DTCT_ACTIONS 0x098
> +#define QPHY_PCIE_V6_30_PCS_EQ_CONFIG1 0x0a8
> +#define QPHY_PCIE_V6_30_PCS_G3_RXEQEVAL_TIME 0x0f8
> +#define QPHY_PCIE_V6_30_PCS_G4_RXEQEVAL_TIME 0x0fc
> +#define QPHY_PCIE_V6_30_PCS_G4_EQ_CONFIG5 0x110
> +#define QPHY_PCIE_V6_30_PCS_G4_PRE_GAIN 0x164
> +#define QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG1 0x184
> +#define QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG3 0x18c
> +#define QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG5 0x194
> +#define QPHY_PCIE_V6_30_PCS_G3_FOM_EQ_CONFIG5 0x1b4
> +#define QPHY_PCIE_V6_30_PCS_G4_FOM_EQ_CONFIG5 0x1c8

There is no user of these. Squash it with the user, because there is
little point in adding dead code.

Best regards,
Krzysztof