[PATCH 7/8] arm64: dts: qcom: x1e80100-qcp: Add power supply and sideband signal for pcie3

Qiang Yu
2024-08-27T06:37:10Z

Add perst, wake and clkreq gpio config. Add required power supply.

Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
---
arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 116 ++++++++++++++++++++++
1 file changed, 116 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts
index 1c3a6a7b3ed6..0deb0c4bfea9 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts
+++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts
@@ -254,6 +254,48 @@ vreg_nvme: regulator-nvme {
pinctrl-names = "default";
pinctrl-0 = <&nvme_reg_en>;
};
+
+ vreg_pcie_12v: regulator-pcie_12v {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_PCIE_12V";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+
+ gpio = <&pm8550ve_8_gpios 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_x8_12v>;
+ };
+
+ vreg_pcie_3v3_aux: regulator-pcie_3v3_aux {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_PCIE_3P3_AUX";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&pmc8380_3_gpios 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pm_sde7_aux_3p3_en>;
+ };
+
+ vreg_pcie_3v3: regulator-pcie_3v3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_PCIE_3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&pmc8380_3_gpios 6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pm_sde7_main_3p3_en>;
+ };
};

&apps_rsc {
@@ -667,6 +709,57 @@ &mdss_dp3_phy {
status = "okay";
};

+&pm8550ve_8_gpios {
+ pcie_x8_12v: pcie_x8_12v_on {
+ pins = "gpio8";
+ function = "normal";
+ output-enable;
+ output-high;
+ bias-pull-down;
+ power-source = <0>;
+ };
+};
+
+&pmc8380_3_gpios {
+ pm_sde7_aux_3p3_en: pm_sde7_aux_3p3 {
+ pins = "gpio8";
+ function = "normal";
+ output-enable;
+ output-high;
+ bias-pull-down;
+ power-source = <0>;
+ };
+
+ pm_sde7_main_3p3_en: pm_sde7_main_3p3 {
+ pins = "gpio6";
+ function = "normal";
+ output-enable;
+ output-high;
+ bias-pull-down;
+ power-source = <0>;
+ };
+};
+
+&pcie3 {
+ vpcie12v-supply = <&vreg_pcie_12v>;
+ vpcie3v3-supply = <&vreg_pcie_3v3>;
+ vpcie3v3aux-supply = <&vreg_pcie_3v3_aux>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3_default>;
+ perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pcie3_phy {
+ vdda-phy-supply = <&vreg_l3j_0p8>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+ vdda-qref-supply = <&vreg_l3c_0p8>;
+
+ status = "okay";
+};
+
&pcie4 {
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
@@ -824,6 +917,29 @@ nvme_reg_en: nvme-reg-en-state {
bias-disable;
};

+ pcie3_default: pcie3-default-state {
+ clkreq-n-pins {
+ pins = "gpio144";
+ function = "pcie3_clk";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio143";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ wake-n-pins {
+ pins = "gpio145";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
pcie4_default: pcie4-default-state {
clkreq-n-pins {
pins = "gpio147";
--
2.34.1