Serverworks LE and MTRR write-combining question

Serverworks LE and MTRR write-combining question

[Mike Russo]

Hello,

I'd like to begin by humbly thanking everyone who works on the kernel 
for their time and patience and energy. Without you my company would 
have had to spend a lot more on software and gotten nowhere near as much 
value in return!

I have a question regarding my motherboard's serverworks LE chipset and 
MTRR write-combining.
/usr/src/linux/arch/i386/kernel/cpu/mtrr/main.c will not allow 
write-combining because of the potential for data corruption,
but according to the following old LKML post, this is only true for 
certain old revisions of the motherboard:

http://www.ussg.iu.edu/hypermail/linux/kernel/0104.3/1007.html

This person even submitted a patch which looked like it was going to be 
accepted, but nothing happened after that. I checked the output of lspci 
and my revision (06) was the first one where the fix was included, 
according to this person's post. I therefore disabled the check and 
recompiled my kernel (2.6.12-rc2-mm3, which is noticeably faster than 
the default fedora core 3 kernel, with nearly the same configuration). X 
was able to setup a write-combining range (I had to disable one that was 
setup already but it didn't seem to affect anything else) and I've been 
working over four hours (wow!) without any corruption or lockups.  Just 
wondering if anyone had any updates on this issue, and if not, hey, 
that's why the source is there -- for me to screw around with. ;)


-- 
Mike Russo
ReadQ Systems, Inc.
(212) 425 3680 x105

Random quote of the day:
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Re: Serverworks LE and MTRR write-combining question

[Lee Revell]

On Thu, 2005-04-14 at 19:00 -0400, Mike Russo wrote:Just 
> wondering if anyone had any updates on this issue, and if not, hey, 
> that's why the source is there -- for me to screw around with. ;)
> 

I think it didn't go in just because no one bothered to repost the patch
with the comment fixed, as requested in that old thread.

Here's the patch from that thread against 2.6.12-rc2.  It also fixes an
unrelated typo in nearby code.  Obviously untested, as I don't have the
hardware ;-)

Summary: Enable write combining for server works LE rev > 6 per
http://www.ussg.iu.edu/hypermail/linux/kernel/0104.3/1007.html

Signed-Off-By: Lee Revell <rlrevell@joe-job.com>

--- linux-2.6.12-rc2-k7/arch/i386/kernel/cpu/mtrr/main.c~	2005-04-14 19:29:31.000000000 -0400
+++ linux-2.6.12-rc2-k7/arch/i386/kernel/cpu/mtrr/main.c	2005-04-14 19:29:16.000000000 -0400
@@ -72,17 +72,21 @@
 static int have_wrcomb(void)
 {
 	struct pci_dev *dev;
+	u8 rev;
 	
 	if ((dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL)) != NULL) {
-		/* ServerWorks LE chipsets have problems with write-combining 
+		/* ServerWorks LE chipsets < rev 6 have problems with write-combining 
 		   Don't allow it and leave room for other chipsets to be tagged */
 		if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
 		    dev->device == PCI_DEVICE_ID_SERVERWORKS_LE) {
-			printk(KERN_INFO "mtrr: Serverworks LE detected. Write-combining disabled.\n");
-			pci_dev_put(dev);
-			return 0;
+			pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
+			if (rev <= 5) {
+				printk(KERN_INFO "mtrr: Serverworks LE rev < 6 detected. Write-combining disabled.\n");
+				pci_dev_put(dev);
+				return 0;
+			}
 		}
-		/* Intel 450NX errata # 23. Non ascending cachline evictions to
+		/* Intel 450NX errata # 23. Non ascending cacheline evictions to
 		   write combining memory may resulting in data corruption */
 		if (dev->vendor == PCI_VENDOR_ID_INTEL &&
 		    dev->device == PCI_DEVICE_ID_INTEL_82451NX) {

Re: Serverworks LE and MTRR write-combining question

[Lee Revell]

On Thu, 2005-04-14 at 19:34 -0400, Lee Revell wrote:
> Here's the patch from that thread against 2.6.12-rc2.  It also fixes an
> unrelated typo in nearby code.  Obviously untested, as I don't have the
> hardware ;-)
> 
> Summary: Enable write combining for server works LE rev > 6 per
> http://www.ussg.iu.edu/hypermail/linux/kernel/0104.3/1007.html

OK, Mike has tested my patch with a rev 6 chipset and report that write
combining works fine.  Andrew, please apply.

Lee