Re: pci cacheline size / latency oddness.

[Jeff Garzik <jgarzik@pobox.com>]

Dave Jones wrote:
> During boot of todays -git, I noticed this..
> 
> PCI: Setting latency timer of device 0000:00:1d.7 to 64
> 
> after boot, lspci shows..
> 
> 00:1d.7 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB2 EHCI Controller (rev 02) (prog-if 20 [EHCI])
> Subsystem: Dell: Unknown device 0169
> Flags: bus master, medium devsel, latency 0, IRQ 201
>                                           ^^						

Probably the hardware doesn't want you to set it, similar to what I 
describe in the following:


> It also complains about..
> 
> PCI: cache line size of 128 is not supported by device 0000:00:1d.7

This message means that it couldn't set the cacheline size at all.  Most 
likely it is either zero, or hardcoded in the silicon.  Has very little 
to do with the platform, and more to do with the device.


> x86-64 doesn't have an arch override for pci_cache_line_size, so
> it ends up at L1_CACHE_BYTES >> 2, which is 128 if you build
> x86-64 kernels with CONFIG_GENERIC_CPU or CONFIG_MPSC
> This means we will do the wrong thing on AMD machines which have
> 64 byte cachelines.   I saw this problem however on an em64t box.
> Would it make sense to shift >> once more if it fails, and retry
> with a smaller size perhaps ?

Too big is far better than too small.

	Jeff