pci cacheline size / latency oddness.

Dave Jones
2005-08-01T23:35:27Z

During boot of todays -git, I noticed this..

PCI: Setting latency timer of device 0000:00:1d.7 to 64

after boot, lspci shows..

00:1d.7 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB2 EHCI Controller (rev 02) (prog-if 20 [EHCI])
Subsystem: Dell: Unknown device 0169
Flags: bus master, medium devsel, latency 0, IRQ 201
^^

It also complains about..

PCI: cache line size of 128 is not supported by device 0000:00:1d.7

x86-64 doesn't have an arch override for pci_cache_line_size, so
it ends up at L1_CACHE_BYTES >> 2, which is 128 if you build
x86-64 kernels with CONFIG_GENERIC_CPU or CONFIG_MPSC
This means we will do the wrong thing on AMD machines which have
64 byte cachelines. I saw this problem however on an em64t box.
Would it make sense to shift >> once more if it fails, and retry
with a smaller size perhaps ?

Dave