Re: pci cacheline size / latency oddness.

Andi Kleen
2005-08-03T10:58:55Z

On Mon, Aug 01, 2005 at 07:35:17PM -0400, Dave Jones wrote:
> During boot of todays -git, I noticed this..
>
> PCI: Setting latency timer of device 0000:00:1d.7 to 64
>
> after boot, lspci shows..
>
> 00:1d.7 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB2 EHCI Controller (rev 02) (prog-if 20 [EHCI])
> Subsystem: Dell: Unknown device 0169
> Flags: bus master, medium devsel, latency 0, IRQ 201
> ^^
>
> It also complains about..
>
> PCI: cache line size of 128 is not supported by device 0000:00:1d.7
>
> x86-64 doesn't have an arch override for pci_cache_line_size, so
> it ends up at L1_CACHE_BYTES >> 2, which is 128 if you build
> x86-64 kernels with CONFIG_GENERIC_CPU or CONFIG_MPSC
> This means we will do the wrong thing on AMD machines which have
> 64 byte cachelines. I saw this problem however on an em64t box.

We should be running arch/i386/pci/common.c:pcibios_init
As far as I can see that should do the right thing on x86-64 too.

> Would it make sense to shift >> once more if it fails, and retry
> with a smaller size perhaps ?

Not sure how much sense it makes to configure a PCI device
to a smaller cache line size than true. Best probably to leave
it alone in this case.

-Andi