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From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: "Maciej W. Rozycki" <macro@orcam.me.uk>
Cc: Bjorn Helgaas <helgaas@kernel.org>,
	linux-pci@vger.kernel.org,  LKML <linux-kernel@vger.kernel.org>,
	 Mika Westerberg <mika.westerberg@linux.intel.com>
Subject: Re: [PATCH 1/2] PCI: Clear LBMS on resume to avoid Target Speed quirk
Date: Fri, 9 Aug 2024 18:55:56 +0300 (EEST)	[thread overview]
Message-ID: <42afa3ee-4429-90e4-9e98-18a0d30c0a3c@linux.intel.com> (raw)
In-Reply-To: <alpine.DEB.2.21.2408091327390.61955@angie.orcam.me.uk>

[-- Attachment #1: Type: text/plain, Size: 2284 bytes --]

On Fri, 9 Aug 2024, Maciej W. Rozycki wrote:

> On Wed, 7 Feb 2024, Ilpo Järvinen wrote:
> 
> > > > > Because if it is constantly picking another speed, it would mean you get 
> > > > > LBMS set over and over again, no? If that happens 34-35 times per second, 
> > > > > it should be set already again when we get into that quirk because there 
> > > > > was some wait before it gets called.
> > > > 
> > > >  I'll see if I can experiment with the hardware over the next couple of 
> > > > days and come back with my findings.
> > > 
> > > Okay thanks.
> > 
> > One point I'd be very interested to know if the link actually comes up 
> > successfully (even if briefly) because this has large implications whether 
> > the quirk can actually be invoked from the bandwidth controller code.
> 
>  That was more than a couple of days, sorry about it.  I have now been 
> able to verify that LBMS keeps getting reasserted over and over again as 
> the device goes through the infinite link training dance.  I haven't ever 
> observed the link to become active in the course.  Here's a short log of 
> commands repeatedly entered at the command prompt:
> 
> # setpci -s 02:03.0 CAP_EXP+0x12.W
> 5011
> # setpci -s 02:03.0 CAP_EXP+0x12.W
> 5812
> # setpci -s 02:03.0 CAP_EXP+0x12.W
> 5811
> # setpci -s 02:03.0 CAP_EXP+0x12.W
> 5812
> # setpci -s 02:03.0 CAP_EXP+0x12.W
> 5011
> # setpci -s 02:03.0 CAP_EXP+0x12.W
> 5811
> # setpci -s 02:03.0 CAP_EXP+0x12.W
> 5811
> # setpci -s 02:03.0 CAP_EXP+0x12.W
> 5812
> # setpci -s 02:03.0 CAP_EXP+0x12.W
> 5812
> # setpci -s 02:03.0 CAP_EXP+0x12.W
> 5811
> # setpci -s 02:03.0 CAP_EXP+0x12.W
> 5811
> # setpci -s 02:03.0 CAP_EXP+0x12.W
> 5812
> # setpci -s 02:03.0 CAP_EXP+0x12.W
> 5812
> # setpci -s 02:03.0 CAP_EXP+0x12.W
> 5811
> 
> As you can see the Link Training bit oscillates as I previously reported 
> and noted in the introduction to `pcie_failed_link_retrain', and also the 
> Current Link Speed field flips between 2.5GT/s and 5GT/s.

Okay, thanks for testing. I suppose that test wasn't done in a busy loop 
(it might not be easy capture very short link up state if there was any 
such period when testing it by manually launching that command a few 
times)?


-- 
 i.

  reply	other threads:[~2024-08-09 15:56 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-29 11:27 [PATCH 0/2] PCI: Fix disconnect related issues Ilpo Järvinen
2024-01-29 11:27 ` [PATCH 1/2] PCI: Clear LBMS on resume to avoid Target Speed quirk Ilpo Järvinen
2024-01-29 18:43   ` Bjorn Helgaas
2024-01-30 11:53     ` Ilpo Järvinen
2024-01-30 16:41       ` Maciej W. Rozycki
2024-01-30 17:33         ` Ilpo Järvinen
2024-02-01  9:47           ` Ilpo Järvinen
2024-02-01 18:49             ` Maciej W. Rozycki
2024-02-02 15:27               ` Ilpo Järvinen
2024-02-07 12:33                 ` Ilpo Järvinen
2024-08-09 13:25                   ` Maciej W. Rozycki
2024-08-09 15:55                     ` Ilpo Järvinen [this message]
2024-08-12 11:59                       ` Maciej W. Rozycki
2024-02-12 17:56               ` Maciej W. Rozycki
2024-01-29 11:27 ` [PATCH 2/2] PCI: Do not wait for disconnected devices when resuming Ilpo Järvinen
2024-01-29 18:55   ` Bjorn Helgaas
2024-01-30 13:15     ` Ilpo Järvinen
2024-02-02 17:03       ` Ilpo Järvinen

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