pci-dma disables iommu on nforce4 motherboards?

pci-dma disables iommu on nforce4 motherboards?

[Ed Sweetman]

I have an asus A8N-E motherboard and recieve the following message on 
boot. 

PCI-DMA: Disabling IOMMU.

I have no issues with anything not functioning.  I guess i'm just 
curious as to why this is done and if i'm missing out on any sort of 
performance gain by not using the iommu.   I have less than 4GB of ram, 
would that be why it's disabled (which is why i think it is)?  

Re: pci-dma disables iommu on nforce4 motherboards?

[Jeff Garzik]

Ed Sweetman wrote:
> I have an asus A8N-E motherboard and recieve the following message on boot.
> PCI-DMA: Disabling IOMMU.
> 
> I have no issues with anything not functioning.  I guess i'm just 
> curious as to why this is done and if i'm missing out on any sort of 
> performance gain by not using the iommu.   I have less than 4GB of ram, 
> would that be why it's disabled (which is why i think it is)?  -

What happens if you boot with iommu=force ?

	Jeff

Re: pci-dma disables iommu on nforce4 motherboards?

[Robert Hancock]

Ed Sweetman wrote:
> I have an asus A8N-E motherboard and recieve the following message on boot.
> PCI-DMA: Disabling IOMMU.
> 
> I have no issues with anything not functioning.  I guess i'm just 
> curious as to why this is done and if i'm missing out on any sort of 
> performance gain by not using the iommu.   I have less than 4GB of ram, 
> would that be why it's disabled (which is why i think it is)?  -

The IOMMU is not needed if your RAM all lies below 4GB (note that due to 
memory space used for PCI and PCI-E resources, even with only 4GB of 
memory, some may end up above 4GB). The purpose of the IOMMU is to allow 
32-bit devices which cannot access memory above 4GB to read from such 
memory. If the system does not have an IOMMU (i.e. the Intel CPUs with 
EM64T) then bounce buffers must be used when these devices want to 
perform DMA to memory above 4GB, which reduces performance.

On some platforms the IOMMU can be used to remap memory such that a 
discontigous memory region appears contiguous to the device, so that it 
can perform DMA transfers in larger chunks. I suspect the performance 
benefit of this is somewhat negated by the time to set up the IOMMU 
mapping, however.

-- 
Robert Hancock      Saskatoon, SK, Canada
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