Re: Dual core Athlons and unsynced TSCs

[Andreas Steinmetz <ast@domdv.de>]

David Lang wrote:
> On Fri, 13 Jan 2006, Sven-Thorsten Dietrich wrote:
> 
>> On Fri, 2006-01-13 at 14:05 -0800, David Lang wrote:
>>
>>> On Fri, 13 Jan 2006 thockin@hockin.org wrote:
>>>
>>>> On Fri, Jan 13, 2006 at 01:18:35PM -0800, David Lang wrote:
>>>>
>>>>> Lee, the last time I saw this discussion I thought it was
>>>>> identified that
>>>>> the multiple cores (or IIRC the multiple chips in a SMP
>>>>> motherboard) would
>>>>> only get out of sync when power management calls were made (hlt or
>>>>> switching the c-state). IIRC the workaround that was posted then
>>>>> was to
>>>>> just disable these in the kernel build.
>>>>
>>>>
>>>> not using 'hlt' when idling means that you spend 10s of Watts more
>>>> power
>>>> on mostly idle systems.
>>>
>>>
>>> true, but for people who need better time accruacy then the other
>>> workaround this may be very acceptable.
>>>
>>
>> 1/4 KW / day for time synchronisation.
>>
>> The power company would love that.
> 
> 
> more precisely 1/4 KW Hour / day
> 
> $0.01 - $0.02/day (I had to lookup the current rates)
> 
> they probably won't notice.
> 

Well, wait until there's AMD based dual core x86_64 laptops out there
(this email being written on a single core x86_64 one). I can already
see the faces of the unhappy future owners being told "use idle=poll"
when on battery and anyway going deaf by fan noise.

(/me ducks and runs)
-- 
Andreas Steinmetz                       SPAMmers use robotrap@domdv.de