From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750997AbWCPNoZ (ORCPT ); Thu, 16 Mar 2006 08:44:25 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1751005AbWCPNoZ (ORCPT ); Thu, 16 Mar 2006 08:44:25 -0500 Received: from ns.protei.ru ([195.239.28.26]:1031 "EHLO mail.protei.ru") by vger.kernel.org with ESMTP id S1750921AbWCPNoZ (ORCPT ); Thu, 16 Mar 2006 08:44:25 -0500 Message-ID: <44196B9A.2020705@protei.ru> Date: Thu, 16 Mar 2006 16:43:54 +0300 From: Nickolay User-Agent: Mozilla Thunderbird 1.0.7 (X11/20050923) X-Accept-Language: en-us, en MIME-Version: 1.0 To: linux-kernel@vger.kernel.org Subject: flushing and invalidating specified cache range in ARM xScale Content-Type: text/plain; charset=KOI8-R; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org Hello Guys! Is there anyway to flush/invalidate specified CPU data cache range in recent kernels? Or i should use ARM DMA interface for allocating memory and forget about direct work with dcache? thanks, Nickolay.