From: Zachary Amsden <zach@vmware.com>
To: Zachary Amsden <zach@vmware.com>
Cc: "Brunner, Richard" <Richard.Brunner@amd.com>,
Nick Piggin <nickpiggin@yahoo.com.au>,
Keir Fraser <Keir.Fraser@cl.cam.ac.uk>,
Hugh Dickins <hugh@veritas.com>,
Jan Beulich <jbeulich@novell.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] i386: PAE entries must have their low word cleared first
Date: Wed, 26 Apr 2006 15:27:15 -0700 [thread overview]
Message-ID: <444FF3C3.8090304@vmware.com> (raw)
In-Reply-To: <444FF2BC.5010504@vmware.com>
Zachary Amsden wrote:
> Brunner, Richard wrote:
>>
>> Maybe the barrier is needed for other architectures, but two writes
>> to WB memory are not going to happen out of order and so no
>> barrier is needed on x86 to the best of my knowledge.
>>
>
> The barrier here is just a compiler barrier - wmb on x86 is just asm
> volatile ("" ::: "memory"); This is needed to stop gcc reordering the
> stores - not because the processor does respect them.
Please forgive my English - and avoiding the double negative - "because
the processor _does_ respect them". And thanks for confirming the
possibility of this bug.
Zach
next prev parent reply other threads:[~2006-04-26 22:33 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-04-26 22:11 [PATCH] i386: PAE entries must have their low word cleared first Brunner, Richard
2006-04-26 22:22 ` Zachary Amsden
2006-04-26 22:27 ` Zachary Amsden [this message]
-- strict thread matches above, loose matches on Subject: below --
2006-04-26 13:46 Jan Beulich
2006-04-26 14:46 ` Hugh Dickins
2006-04-26 15:06 ` Keir Fraser
2006-04-26 15:44 ` Zachary Amsden
2006-04-26 15:57 ` Hugh Dickins
2006-04-26 16:12 ` Keir Fraser
2006-04-26 15:45 ` Hugh Dickins
2006-04-26 16:06 ` Nick Piggin
2006-04-26 15:58 ` Nick Piggin
2006-04-27 10:27 ` Sonny Rao
2006-04-27 13:39 ` Nick Piggin
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