From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932418AbWDZWdx (ORCPT ); Wed, 26 Apr 2006 18:33:53 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S932421AbWDZWdx (ORCPT ); Wed, 26 Apr 2006 18:33:53 -0400 Received: from mailout1.vmware.com ([65.113.40.130]:33297 "EHLO mailout1.vmware.com") by vger.kernel.org with ESMTP id S932418AbWDZWdw (ORCPT ); Wed, 26 Apr 2006 18:33:52 -0400 Message-ID: <444FF3C3.8090304@vmware.com> Date: Wed, 26 Apr 2006 15:27:15 -0700 From: Zachary Amsden User-Agent: Thunderbird 1.5.0.2 (X11/20060420) MIME-Version: 1.0 To: Zachary Amsden Cc: "Brunner, Richard" , Nick Piggin , Keir Fraser , Hugh Dickins , Jan Beulich , linux-kernel@vger.kernel.org Subject: Re: [PATCH] i386: PAE entries must have their low word cleared first References: <99F8FA0D1537DC4EB2A639E8E60D782A6288D0@SAUSEXMB3.amd.com> <444FF2BC.5010504@vmware.com> In-Reply-To: <444FF2BC.5010504@vmware.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org Zachary Amsden wrote: > Brunner, Richard wrote: >> >> Maybe the barrier is needed for other architectures, but two writes >> to WB memory are not going to happen out of order and so no >> barrier is needed on x86 to the best of my knowledge. >> > > The barrier here is just a compiler barrier - wmb on x86 is just asm > volatile ("" ::: "memory"); This is needed to stop gcc reordering the > stores - not because the processor does respect them. Please forgive my English - and avoiding the double negative - "because the processor _does_ respect them". And thanks for confirming the possibility of this bug. Zach