From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932706AbbESJwT (ORCPT ); Tue, 19 May 2015 05:52:19 -0400 Received: from mout.kundenserver.de ([212.227.17.24]:50357 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932628AbbESJwQ (ORCPT ); Tue, 19 May 2015 05:52:16 -0400 From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org, ganguly.s@samsung.com Cc: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, peterz@infradead.org, Waiman.Long@hp.com, raghavendra.kt@linux.vnet.ibm.com, oleg@redhat.com, linux-kernel@vger.kernel.org, SHARAN ALLUR , torvalds@linux-foundation.org Subject: Re: [RFC] arm: Add for atomic half word exchange Date: Tue, 19 May 2015 11:51:21 +0200 Message-ID: <4497461.dn0jdrPFfy@wuerfel> User-Agent: KMail/4.11.5 (Linux/3.16.0-10-generic; KDE/4.11.5; x86_64; ; ) In-Reply-To: <1122007906.400701432028368414.JavaMail.weblogic@ep2mlwas07a> References: <1122007906.400701432028368414.JavaMail.weblogic@ep2mlwas07a> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Provags-ID: V03:K0:5WeGhaeBEDOs8k/kzXl4w5UC9AuSJ2516Xt/F7XgjiwFaTIgPFt 1vtHF93xKVSzhTK690vPKYKLoY2D2flpZc/+V5oD5UjZhc5sl9S/Bfa14lJgBghQxrAjm7a OWO7fNwsPIDYF4NdoilIXCoCSqxVYmbEw37LtjSIgpV3r/EOFu1fF6MHJ+SW+MNG4zig202 svLllb2P7TO9X92lFiE4w== X-UI-Out-Filterresults: notjunk:1; Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tuesday 19 May 2015 09:39:33 Sarbojit Ganguly wrote: > Since 16 bit half word exchange was not there and MCS based qspinlock by Waiman's xchg_tail() requires an atomic exchange on a half word, > here is a small modification to __xchg() code. We have discussed a similar patch before, see https://lkml.org/lkml/2015/2/25/390 > #if __LINUX_ARM_ARCH__ >= 6 > @@ -50,6 +52,23 @@ > : "r" (x), "r" (ptr) > : "memory", "cc"); > break; > + /* > + * halfword exclusive exchange > + * This is new implementation as qspinlock > + * wants 16 bit atomic CAS. > + */ > + case 2: > + asm volatile("@ __xchg2\n" > + "1: ldrexh %0, [%3]\n" > + " strexh %1, %2, [%3]\n" > + " teq %1, #0\n" > + " bne 1b" > + : "=&r" (ret), "=&r" (tmp) > + : "r" (x), "r" (ptr) > + : "memory", "cc"); > + break; > case 4: > asm volatile("@ __xchg4\n" > "1: ldrex %0, [%3]\n" Please try to find a way to make this compile when CONFIG_CPU_V6 is set. Arnd