[PATCH v5 0/4] Patches to add support for Rockchip dwc2 controller

[PATCH v5 0/4] Patches to add support for Rockchip dwc2 controller

[Kever Yang]

These patches to add support for dwc2 controller found in
Rockchip processors rk3066, rk3188 and rk3288,
and enable dts for rk3288 evb.

Changes in v5:
- max_transfer_size change to 65535 to met the requirement of
  header file
- change the sort order of dwc2 in rk3288.dtsi
- don't enable otg port for evb

Changes in v4:
- max_transfer_size change to 65536, this should be enough
  for most transfer, the hardware auto-detect will set this
  to 0x7ffff which may make dma_alloc_coherent fail when
  non-dword aligned buf from driver like usbnet happen.
- remove EHCI and HSIC dts patch for Doug had post it seprately.

Changes in v3:
- EHCI and HSIC move new for version 3.
- Rebase

Changes in v2:
- Split out dr_mode and rk3288 bindings.
- add compatible "snps,dwc2" bingding info
- set most parameters as driver auto-detect
- evb patch added in version 2

Kever Yang (4):
  Documentation: dt-bindings: add dt binding info for Rockchip dwc2
  usb: dwc2: add compatible data for rockchip soc
  ARM: dts: add rk3288 dwc2 controller support
  ARM: dts: Enable USB host1(dwc) on rk3288-evb

 Documentation/devicetree/bindings/usb/dwc2.txt |  3 +++
 arch/arm/boot/dts/rk3288-evb.dtsi              |  4 ++++
 arch/arm/boot/dts/rk3288.dtsi                  | 20 ++++++++++++++++++
 drivers/usb/dwc2/platform.c                    | 29 ++++++++++++++++++++++++++
 4 files changed, 56 insertions(+)

-- 
1.9.1

[PATCH v5 1/4] Documentation: dt-bindings: add dt binding info for Rockchip dwc2

[Kever Yang]

This add necessary dwc2 binding documentation for Rockchip socs:
rk3066, rk3188 and rk3288

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- add compatible "snps,dwc2" bingding info

 Documentation/devicetree/bindings/usb/dwc2.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt
index 467ddd1..2899679 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
@@ -4,6 +4,9 @@ Platform DesignWare HS OTG USB 2.0 controller
 Required properties:
 - compatible : One of:
   - brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC.
+  - rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc;
+  - "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc;
+  - "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc;
   - snps,dwc2: A generic DWC2 USB controller with default parameters.
 - reg : Should contain 1 register range (address and length)
 - interrupts : Should contain 1 interrupt
-- 
1.9.1

Re: [PATCH v5 1/4] Documentation: dt-bindings: add dt binding info for Rockchip dwc2

[Doug Anderson]

Kever,

On Thu, Aug 7, 2014 at 8:55 PM, Kever Yang <kever.yang@rock-chips.com> wrote:
> This add necessary dwc2 binding documentation for Rockchip socs:
> rk3066, rk3188 and rk3288
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Acked-by: Stephen Warren <swarren@nvidia.com>
> ---
>
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - Split out dr_mode and rk3288 bindings.
> - add compatible "snps,dwc2" bingding info
>
>  Documentation/devicetree/bindings/usb/dwc2.txt | 3 +++
>  1 file changed, 3 insertions(+)

IMHO this series is ready to go in for 3.18 whenever maintainers feel
it's the right time.

Reviewed-by: Doug Anderson <dianders@chromium.org>

[PATCH v5 2/4] usb: dwc2: add compatible data for rockchip soc

[Kever Yang]

This patch add compatible data for dwc2 controller found on
rk3066, rk3188 and rk3288 processors from rockchip.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Paul Zimmerman <paulz@synopsys.com>
---

Changes in v5:
- max_transfer_size change to 65535 to met the requirement of
  header file

Changes in v4:
- max_transfer_size change to 65536, this should be enough
  for most transfer, the hardware auto-detect will set this
  to 0x7ffff which may make dma_alloc_coherent fail when
  non-dword aligned buf from driver like usbnet happen.

Changes in v3: None
Changes in v2:
- set most parameters as driver auto-detect

 drivers/usb/dwc2/platform.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index a10e7a3..2f859bd 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -75,6 +75,34 @@ static const struct dwc2_core_params params_bcm2835 = {
 	.uframe_sched			= 0,
 };
 
+static const struct dwc2_core_params params_rk3066 = {
+	.otg_cap			= 2,	/* non-HNP/non-SRP */
+	.otg_ver			= -1,
+	.dma_enable			= -1,
+	.dma_desc_enable		= 0,
+	.speed				= -1,
+	.enable_dynamic_fifo		= 1,
+	.en_multiple_tx_fifo		= -1,
+	.host_rx_fifo_size		= 520,	/* 520 DWORDs */
+	.host_nperio_tx_fifo_size	= 128,	/* 128 DWORDs */
+	.host_perio_tx_fifo_size	= 256,	/* 256 DWORDs */
+	.max_transfer_size		= 65535,
+	.max_packet_count		= -1,
+	.host_channels			= -1,
+	.phy_type			= -1,
+	.phy_utmi_width			= -1,
+	.phy_ulpi_ddr			= -1,
+	.phy_ulpi_ext_vbus		= -1,
+	.i2c_enable			= -1,
+	.ulpi_fs_ls			= -1,
+	.host_support_fs_ls_low_power	= -1,
+	.host_ls_low_power_phy_clk	= -1,
+	.ts_dline			= -1,
+	.reload_ctl			= -1,
+	.ahbcfg				= 0x7, /* INCR16 */
+	.uframe_sched			= -1,
+};
+
 /**
  * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
  * DWC_otg driver
@@ -97,6 +125,7 @@ static int dwc2_driver_remove(struct platform_device *dev)
 
 static const struct of_device_id dwc2_of_match_table[] = {
 	{ .compatible = "brcm,bcm2835-usb", .data = &params_bcm2835 },
+	{ .compatible = "rockchip,rk3066-usb", .data = &params_rk3066 },
 	{ .compatible = "snps,dwc2", .data = NULL },
 	{},
 };
-- 
1.9.1

Re: [PATCH v5 2/4] usb: dwc2: add compatible data for rockchip soc

[Doug Anderson]

Kever

On Thu, Aug 7, 2014 at 8:55 PM, Kever Yang <kever.yang@rock-chips.com> wrote:
> This patch add compatible data for dwc2 controller found on
> rk3066, rk3188 and rk3288 processors from rockchip.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Acked-by: Paul Zimmerman <paulz@synopsys.com>
> ---
>
> Changes in v5:
> - max_transfer_size change to 65535 to met the requirement of
>   header file
>
> Changes in v4:
> - max_transfer_size change to 65536, this should be enough
>   for most transfer, the hardware auto-detect will set this
>   to 0x7ffff which may make dma_alloc_coherent fail when
>   non-dword aligned buf from driver like usbnet happen.
>
> Changes in v3: None
> Changes in v2:
> - set most parameters as driver auto-detect
>
>  drivers/usb/dwc2/platform.c | 29 +++++++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)

IMHO this series is ready to go in for 3.18 whenever maintainers feel
it's the right time.

Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>

[PATCH v5 3/4] ARM: dts: add rk3288 dwc2 controller support

[Kever Yang]

rk3288 has two kind of usb controller, this add the dwc2 controller
for otg and host1.

Controller can works with usb PHY default setting and Vbus on.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
---

Changes in v5:
- change the sort order of dwc2 in rk3288.dtsi

Changes in v4: None
Changes in v3:
- EHCI and HSIC move new for version 3.

Changes in v2: None

 arch/arm/boot/dts/rk3288.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 5950b0a..58167f1 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -206,6 +206,26 @@
 
 	/* NOTE: ohci@ff520000 doesn't actually work on hardware */
 
+	usb_host1: usb@ff540000 {
+		compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
+				"snps,dwc2";
+		reg = <0xff540000 0x40000>;
+		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_USBHOST1>;
+		clock-names = "otg";
+		status = "disabled";
+	};
+
+	usb_otg: usb@ff580000 {
+		compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
+				"snps,dwc2";
+		reg = <0xff580000 0x40000>;
+		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_OTG0>;
+		clock-names = "otg";
+		status = "disabled";
+	};
+
 	usb_hsic: usb@ff5c0000 {
 		compatible = "generic-ehci";
 		reg = <0xff5c0000 0x100>;
-- 
1.9.1

Re: [PATCH v5 3/4] ARM: dts: add rk3288 dwc2 controller support

[Doug Anderson]

Kever,

On Thu, Aug 7, 2014 at 8:55 PM, Kever Yang <kever.yang@rock-chips.com> wrote:
> rk3288 has two kind of usb controller, this add the dwc2 controller
> for otg and host1.
>
> Controller can works with usb PHY default setting and Vbus on.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Reviewed-by: Doug Anderson <dianders@chromium.org>
> Tested-by: Doug Anderson <dianders@chromium.org>
> ---
>
> Changes in v5:
> - change the sort order of dwc2 in rk3288.dtsi
>
> Changes in v4: None
> Changes in v3:
> - EHCI and HSIC move new for version 3.
>
> Changes in v2: None
>
>  arch/arm/boot/dts/rk3288.dtsi | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)

IMHO this series is ready to go in for 3.18.  I'm assuming Heiko will
pick it up once the bindings have landed.  It already has my tags.  ;)

Re: [PATCH v5 3/4] ARM: dts: add rk3288 dwc2 controller support

[Heiko Stübner]

Am Freitag, 8. August 2014, 08:45:16 schrieb Doug Anderson:
> Kever,
> 
> On Thu, Aug 7, 2014 at 8:55 PM, Kever Yang <kever.yang@rock-chips.com> 
wrote:
> > rk3288 has two kind of usb controller, this add the dwc2 controller
> > for otg and host1.
> > 
> > Controller can works with usb PHY default setting and Vbus on.
> > 
> > Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> > Reviewed-by: Doug Anderson <dianders@chromium.org>
> > Tested-by: Doug Anderson <dianders@chromium.org>
> > ---
> > 
> > Changes in v5:
> > - change the sort order of dwc2 in rk3288.dtsi
> > 
> > Changes in v4: None
> > Changes in v3:
> > - EHCI and HSIC move new for version 3.
> > 
> > Changes in v2: None
> > 
> >  arch/arm/boot/dts/rk3288.dtsi | 20 ++++++++++++++++++++
> >  1 file changed, 20 insertions(+)
> 
> IMHO this series is ready to go in for 3.18.  I'm assuming Heiko will
> pick it up once the bindings have landed.  It already has my tags.  ;)

correct ... the dts changes look ok, so I'll take patches 3 and 4 once patches 
1 and 2 are included somewhere.


Heiko

Re: [PATCH v5 3/4] ARM: dts: add rk3288 dwc2 controller support

[Heiko Stübner]

Am Freitag, 8. August 2014, 17:53:45 schrieb Heiko Stübner:
> Am Freitag, 8. August 2014, 08:45:16 schrieb Doug Anderson:
> > Kever,
> > 
> > On Thu, Aug 7, 2014 at 8:55 PM, Kever Yang <kever.yang@rock-chips.com>
> 
> wrote:
> > > rk3288 has two kind of usb controller, this add the dwc2 controller
> > > for otg and host1.
> > > 
> > > Controller can works with usb PHY default setting and Vbus on.
> > > 
> > > Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> > > Reviewed-by: Doug Anderson <dianders@chromium.org>
> > > Tested-by: Doug Anderson <dianders@chromium.org>
> > > ---
> > > 
> > > Changes in v5:
> > > - change the sort order of dwc2 in rk3288.dtsi
> > > 
> > > Changes in v4: None
> > > Changes in v3:
> > > - EHCI and HSIC move new for version 3.
> > > 
> > > Changes in v2: None
> > > 
> > >  arch/arm/boot/dts/rk3288.dtsi | 20 ++++++++++++++++++++
> > >  1 file changed, 20 insertions(+)
> > 
> > IMHO this series is ready to go in for 3.18.  I'm assuming Heiko will
> > pick it up once the bindings have landed.  It already has my tags.  ;)
> 
> correct ... the dts changes look ok, so I'll take patches 3 and 4 once
> patches 1 and 2 are included somewhere.
> 

I've added patches 3 and 4 to my v3.18-next/dts branch

[PATCH v5 4/4] ARM: dts: Enable USB host1(dwc) on rk3288-evb

[Kever Yang]

USB host1 port is the host A port nearby the otg port.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

---

Changes in v5:
- don't enable otg port for evb

Changes in v4: None
Changes in v3:
- Rebase

Changes in v2:
- evb patch added in version 2

 arch/arm/boot/dts/rk3288-evb.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
index 4f57209..4b62df6 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -94,3 +94,7 @@
 &usb_host0_ehci {
 	status = "okay";
 };
+
+&usb_host1 {
+	status = "okay";
+};
-- 
1.9.1

Re: [PATCH v5 4/4] ARM: dts: Enable USB host1(dwc) on rk3288-evb

[Doug Anderson]

Kever,

On Thu, Aug 7, 2014 at 8:55 PM, Kever Yang <kever.yang@rock-chips.com> wrote:
> USB host1 port is the host A port nearby the otg port.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>
> ---
>
> Changes in v5:
> - don't enable otg port for evb
>
> Changes in v4: None
> Changes in v3:
> - Rebase
>
> Changes in v2:
> - evb patch added in version 2
>
>  arch/arm/boot/dts/rk3288-evb.dtsi | 4 ++++
>  1 file changed, 4 insertions(+)

IMHO this series is ready to go in for 3.18.  I'm assuming Heiko will
pick it up once the bindings have landed.

Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>

Re: [PATCH v5 0/4] Patches to add support for Rockchip dwc2 controller

[Heiko Stübner]

Hi Greg,

Am Freitag, 8. August 2014, 11:55:55 schrieb Kever Yang:
> These patches to add support for dwc2 controller found in
> Rockchip processors rk3066, rk3188 and rk3288,
> and enable dts for rk3288 evb.

will you take patches 1 and 2?


Thanks
Heiko


> 
> Changes in v5:
> - max_transfer_size change to 65535 to met the requirement of
>   header file
> - change the sort order of dwc2 in rk3288.dtsi
> - don't enable otg port for evb
> 
> Changes in v4:
> - max_transfer_size change to 65536, this should be enough
>   for most transfer, the hardware auto-detect will set this
>   to 0x7ffff which may make dma_alloc_coherent fail when
>   non-dword aligned buf from driver like usbnet happen.
> - remove EHCI and HSIC dts patch for Doug had post it seprately.
> 
> Changes in v3:
> - EHCI and HSIC move new for version 3.
> - Rebase
> 
> Changes in v2:
> - Split out dr_mode and rk3288 bindings.
> - add compatible "snps,dwc2" bingding info
> - set most parameters as driver auto-detect
> - evb patch added in version 2
> 
> Kever Yang (4):
>   Documentation: dt-bindings: add dt binding info for Rockchip dwc2
>   usb: dwc2: add compatible data for rockchip soc
>   ARM: dts: add rk3288 dwc2 controller support
>   ARM: dts: Enable USB host1(dwc) on rk3288-evb
> 
>  Documentation/devicetree/bindings/usb/dwc2.txt |  3 +++
>  arch/arm/boot/dts/rk3288-evb.dtsi              |  4 ++++
>  arch/arm/boot/dts/rk3288.dtsi                  | 20 ++++++++++++++++++
>  drivers/usb/dwc2/platform.c                    | 29
> ++++++++++++++++++++++++++ 4 files changed, 56 insertions(+)