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        id 1nhBtC-0006R6-OT; Wed, 20 Apr 2022 17:05:06 +0200
From:   Heiko Stuebner <heiko@sntech.de>
To:     linux-gpio@vger.kernel.org,
        Luca Ceresoli <luca.ceresoli@bootlin.com>
Cc:     Luca Ceresoli <luca.ceresoli@bootlin.com>,
        Linus Walleij <linus.walleij@linaro.org>,
        Jianqun Xu <jay.xu@rock-chips.com>,
        linux-arm-kernel@lists.infradead.org,
        linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] pinctrl: rockchip: sort the rk3308_mux_recalced_data entries
Date:   Wed, 20 Apr 2022 17:05:06 +0200
Message-ID: <4520799.LvFx2qVVIh@phil>
In-Reply-To: <20220420142432.248565-2-luca.ceresoli@bootlin.com>
References: <20220420142432.248565-1-luca.ceresoli@bootlin.com> <20220420142432.248565-2-luca.ceresoli@bootlin.com>
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Am Mittwoch, 20. April 2022, 16:24:32 CEST schrieb Luca Ceresoli:
> All the entries are sorted according to num/pin except for two
> entries. Sort them too.
> 
> Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

> ---
>  drivers/pinctrl/pinctrl-rockchip.c | 28 ++++++++++++++--------------
>  1 file changed, 14 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
> index 65fa305b5f59..2cb79e649fcf 100644
> --- a/drivers/pinctrl/pinctrl-rockchip.c
> +++ b/drivers/pinctrl/pinctrl-rockchip.c
> @@ -512,20 +512,6 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
>  		.reg = 0x34,
>  		.bit = 8,
>  		.mask = 0xf
> -	}, {
> -		/* gpio3b4_sel */
> -		.num = 3,
> -		.pin = 12,
> -		.reg = 0x68,
> -		.bit = 8,
> -		.mask = 0xf
> -	}, {
> -		/* gpio3b5_sel */
> -		.num = 3,
> -		.pin = 13,
> -		.reg = 0x68,
> -		.bit = 12,
> -		.mask = 0xf
>  	}, {
>  		/* gpio2a2_sel */
>  		.num = 2,
> @@ -561,6 +547,20 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
>  		.reg = 0x68,
>  		.bit = 6,
>  		.mask = 0x3
> +	}, {
> +		/* gpio3b4_sel */
> +		.num = 3,
> +		.pin = 12,
> +		.reg = 0x68,
> +		.bit = 8,
> +		.mask = 0xf
> +	}, {
> +		/* gpio3b5_sel */
> +		.num = 3,
> +		.pin = 13,
> +		.reg = 0x68,
> +		.bit = 12,
> +		.mask = 0xf
>  	},
>  };
>  
>