From: "H. Peter Anvin" <hpa@zytor.com>
To: "Rafael J. Wysocki" <rjw@sisk.pl>
Cc: Sandeep Kumar <sandeepksinha@gmail.com>, linux-kernel@vger.kernel.org
Subject: Re: PAE and PSE ??
Date: Mon, 23 Oct 2006 07:10:38 -0700 [thread overview]
Message-ID: <453CCD5E.6060303@zytor.com> (raw)
In-Reply-To: <200610231213.47232.rjw@sisk.pl>
Rafael J. Wysocki wrote:
>
> Well, "AMD64 Architecture Programmer’s Manual" says the following:
>
> The choice of 2 Mbyte or 4 Mbyte as the large physical-page size
> depends on the value of CR4.PSE and CR4.PAE, as follows:
> - If physical-address extensions are enabled (CR4.PAE=1), the
> large physical-page size is 2 Mbytes, regardless of the value
> of CR4.PSE.
> - If physical-address extensions are disabled (CR4.PAE=0)
> and CR4.PSE=1, the large physical-page size is 4 Mbytes.
> - If both CR4.PAE=0 and CR4.PSE=0, the only available page
> size is 4 Kbytes.
>
That would be a retroactive redef on the part of AMD; it probably makes
sense for x86-64 if someone thinks that is may drop support for 4 MB
pages at some point in the distant future. Still, I'm not sure Intel
would agree with the definition as stated, although I haven't looked in
the docs.
This is all extremely theoretical, since there has never been a chip
with PAE=1 and PSE=0, and I wouldn't expect one to appear any time soon.
-hpa
next prev parent reply other threads:[~2006-10-23 14:10 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-10-22 6:29 PAE and PSE ?? Sandeep Kumar
2006-10-22 10:15 ` Rafael J. Wysocki
2006-10-22 23:37 ` H. Peter Anvin
2006-10-23 10:13 ` Rafael J. Wysocki
2006-10-23 14:10 ` H. Peter Anvin [this message]
2006-10-23 14:14 ` Rafael J. Wysocki
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