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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa6260ebaabsm142014466b.198.2024.12.05.13.36.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Dec 2024 13:36:12 -0800 (PST) Message-ID: <45643708-c138-4c77-85ce-fa7d49f2aa72@oss.qualcomm.com> Date: Thu, 5 Dec 2024 22:36:11 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] arm64: dts: qcom: qcs8300: add DisplayPort device nodes To: Yongxing Mou , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ritesh Kumar References: <20241127-dp_dts_qcs8300-v1-0-e3d13dec4233@quicinc.com> <20241127-dp_dts_qcs8300-v1-1-e3d13dec4233@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20241127-dp_dts_qcs8300-v1-1-e3d13dec4233@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: Y-L1AB41y8uEvSKei9Ux467XsnsmIwFS X-Proofpoint-ORIG-GUID: Y-L1AB41y8uEvSKei9Ux467XsnsmIwFS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 phishscore=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 suspectscore=0 mlxlogscore=996 malwarescore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412050161 On 27.11.2024 11:45 AM, Yongxing Mou wrote: > Add device tree nodes for the DPTX0 controller with their > corresponding PHYs found on Qualcomm QCS8300 SoC. > > Signed-off-by: Yongxing Mou > --- > arch/arm64/boot/dts/qcom/qcs8300.dtsi | 115 +++++++++++++++++++++++++++++++++- > 1 file changed, 114 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi > index 1642e2863affd5af0b4f68118a47b7a74b76df95..28deba0a389641b4dddbf4505d6f44c6607aa03b 100644 > --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi > @@ -987,6 +987,19 @@ mdss_mdp: display-controller@ae01000 { > interrupt-parent = <&mdss>; > interrupts = <0>; > > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + dpu_intf0_out: endpoint { > + remote-endpoint = <&mdss_dp0_in>; > + }; > + }; > + }; > + > mdp_opp_table: opp-table { > compatible = "operating-points-v2"; > > @@ -1011,6 +1024,104 @@ opp-650000000 { > }; > }; > }; > + > + mdss_dp0_phy: phy@aec2a00 { > + compatible = "qcom,qcs8300-edp-phy"; > + > + reg = <0x0 0x0aec2a00 0x0 0x200>, 0x19c > + <0x0 0x0aec2200 0x0 0xd0>, 0xec > + <0x0 0x0aec2600 0x0 0xd0>, 0xec For lengths > + <0x0 0x0aec2000 0x0 0x1c8>; This one's correct > + > + clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, > + <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>; > + clock-names = "aux", > + "cfg_ahb"; power-domains = <&rpmhpd RPMHPD_MX>; (or maybe even MXC?) > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > + mdss_dp0: displayport-controller@af54000 { > + compatible = "qcom,qcs8300-dp"; > + > + reg = <0x0 0x0af54000 0x0 0x104>, 0x200 > + <0x0 0x0af54200 0x0 0x0c0>, 0x200 > + <0x0 0x0af55000 0x0 0x770>, 0xc00 > + <0x0 0x0af56000 0x0 0x09c>; 0x400 for lengths Konrad