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Sun, 16 Nov 2025 03:01:10 -0800 (PST) Message-ID: <456bba04-07b7-4c27-96fc-9bf226b12fd9@gmail.com> Date: Sun, 16 Nov 2025 16:31:04 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4] arm64: errata: Work around AmpereOne's erratum AC04_CPU_23 Content-Language: en-US To: D Scott Phillips , Catalin Marinas , James Clark , James Morse , Joey Gouly , Kevin Brodsky , Marc Zyngier , Mark Brown , Mark Rutland , Oliver Upton , "Rob Herring (Arm)" , Shameer Kolothum , Shiqi Liu , Will Deacon , Yicong Yang , kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20250513184514.2678288-1-scott@os.amperecomputing.com> From: Jaikiran Pai In-Reply-To: <20250513184514.2678288-1-scott@os.amperecomputing.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hello Scott, On 14/05/25 12:15 am, D Scott Phillips wrote: > On AmpereOne AC04, updates to HCR_EL2 can rarely corrupt simultaneous > translations for data addresses initiated by load/store instructions. > Only instruction initiated translations are vulnerable, not translations > from prefetches for example. A DSB before the store to HCR_EL2 is > sufficient to prevent older instructions from hitting the window for > corruption, and an ISB after is sufficient to prevent younger > instructions from hitting the window for corruption. I see that this patch enables the workaround only for AmpereOne AC04 systems. Do you happen to know if the underlying issue for which this patch was introduced, impacts (or can impact) AmpereOne AC03 systems too: CPU implementer    : 0xc0 CPU architecture: 8 CPU variant    : 0x0 CPU part    : 0xac3 CPU revision    : 1 -Jaikiran