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[86.58.6.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439922141a5sm32958965e9.2.2025.02.18.09.23.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Feb 2025 09:23:56 -0800 (PST) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Chen-Yu Tsai , Samuel Holland , Alex Studer Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Alex Studer Subject: Re: [PATCH] riscv: dts: allwinner: d1: Add CPU thermal sensor and zone Date: Tue, 18 Feb 2025 18:23:52 +0100 Message-ID: <4628970.LvFx2qVVIh@jernej-laptop> In-Reply-To: <20250218020629.1476126-1-alex@studer.dev> References: <20250218020629.1476126-1-alex@studer.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne torek, 18. februar 2025 ob 03:06:29 Srednjeevropski standardni =C4=8Das= je Alex Studer napisal(a): > The sun20i THS (built in CPU thermal sensor) is supported in code, but > was never added to the device tree. So, add it to the device tree, > along with a thermal zone for the CPU. >=20 > Signed-off-by: Alex Studer > --- > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 31 +++++++++++++++++++ > .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 16 ++++++++++ > 2 files changed, 47 insertions(+) >=20 > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/b= oot/dts/allwinner/sun20i-d1s.dtsi > index 6367112e6..bdde82aa8 100644 > --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > @@ -3,6 +3,8 @@ > =20 > #define SOC_PERIPHERAL_IRQ(nr) (nr + 16) > =20 > +#include Put above line on top (before SOC_PERIPHERAL_IRQ()). > + > #include "sunxi-d1s-t113.dtsi" > =20 > / { > @@ -115,4 +117,33 @@ pmu { > <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>, > <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>; > }; > + > + thermal-zones { > + cpu-thermal { > + polling-delay-passive =3D <0>; > + polling-delay =3D <0>; > + thermal-sensors =3D <&ths>; > + > + cooling-maps { > + map0 { > + trip =3D <&cpu_alert>; > + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > + > + trips { > + cpu_alert: cpu-alert { > + temperature =3D <85000>; > + hysteresis =3D <2000>; > + type =3D "passive"; > + }; > + > + cpu-crit { > + temperature =3D <100000>; > + hysteresis =3D <0>; > + type =3D "critical"; > + }; Where do those limits come from? > + }; > + }; > + }; > }; > diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/ris= cv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > index e4175adb0..fcfcaf06c 100644 > --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > @@ -426,6 +426,10 @@ sid: efuse@3006000 { > reg =3D <0x3006000 0x1000>; > #address-cells =3D <1>; > #size-cells =3D <1>; > + > + ths_calibration: thermal-sensor-calibration@14 { > + reg =3D <0x14 0x8>; > + }; > }; > =20 > crypto: crypto@3040000 { > @@ -934,5 +938,17 @@ rtc: rtc@7090000 { > clock-names =3D "bus", "hosc", "ahb"; > #clock-cells =3D <1>; > }; > + > + ths: thermal-sensor@2009400 { > + compatible =3D "allwinner,sun20i-d1-ths"; > + reg =3D <0x2009400 0x100>; Size should be 0x400. Best regards, Jernej > + interrupts =3D ; > + clocks =3D <&ccu CLK_BUS_THS>; > + clock-names =3D "bus"; > + resets =3D <&ccu RST_BUS_THS>; > + nvmem-cells =3D <&ths_calibration>; > + nvmem-cell-names =3D "calibration"; > + #thermal-sensor-cells =3D <0>; > + }; > }; > }; >=20