From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5335C401A01 for ; Mon, 11 May 2026 18:31:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778524298; cv=none; b=FUt96RM0iGIAwQF21iXrmVGzTpBaW836iCE+K6785+4ZQe5SHMjVaAFLqxMfTvSKSRju/IFT779TaT2j50Ntlt4kgzraCeRkfxLywdHSPr8n+yw9WGgQ3WdqUIniEb3Pnibu5zTY2sSeKcrrZ8mq7D8OCYWitYTpx18OqlNh2Z4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778524298; c=relaxed/simple; bh=yAroUwZ0Px8ARskG4DqFPBVU8jY00U9EJFO3vig1K9Q=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=LwHoCfGyh8IlRb0DnnCwRwGbFlr1r3Qdl9ZjBYhQL7tpNXGgjpVi43FCzOysVaXDvF+QfiUqCzGX5SZNNCnt+rEv4vanGkgtpGMUeI2NYmWhWzDKMMK+XkIoIEIUa6E/TQZb1yqqI1MHFfu3gBTSlvQyCRO9AmeA66pFR5ge3XE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=GutqXGYO; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="GutqXGYO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1778524295; bh=yAroUwZ0Px8ARskG4DqFPBVU8jY00U9EJFO3vig1K9Q=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=GutqXGYO3JhKA3FnsetFtIbZHyWyyqJkjRYkQEkGaQhIIfwrA757hUQ5q8tn2932k xcpBsfXSaijdhk/XjmUJyOKH/6t5xqVdzv+7G9k6ZiZNsIsD6d333AulhcoTVVXAn3 SdlpoML5KJrnLWxPvM0XxNTjmrTpdNNUBDB0yivI1UZNn0s2X482X4/IcRT3PvK7FD Iacp5x96JzOqR+zydNO6YOS8h26nFHNW9tZHisCS+phOwR9U0BYrSO5O+DeUgxFnZu Laz0qQfL9EL6Ox9BwEDg3I/YU/dJVvq5EUrZStlUAkkh0+AHQpJb/daZPWMlBABYxB DqGluskkQ0Siw== Received: from [100.64.0.241] (unknown [100.64.0.241]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 1F6CF17E12AA; Mon, 11 May 2026 20:31:35 +0200 (CEST) Message-ID: <466dd8c9-c80b-467a-ab99-e58a308079c9@collabora.com> Date: Mon, 11 May 2026 21:31:34 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/6] phy: rockchip: samsung-hdptx: Clock fixes and API transition cleanups To: Vinod Koul Cc: Neil Armstrong , Heiko Stuebner , Algea Cao , Dmitry Baryshkov , kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260227-hdptx-clk-fixes-v1-0-f998f2762d0f@collabora.com> Content-Language: en-US From: Cristian Ciocaltea In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 5/11/26 7:18 PM, Vinod Koul wrote: > On 10-05-26, 11:55, Cristian Ciocaltea wrote: >> Hi Vinod, >> >> On 5/10/26 10:36 AM, Vinod Koul wrote: >>> On 27-02-26, 22:48, Cristian Ciocaltea wrote: >>>> This series provides a set of bug fixes and cleanups for the Rockchip >>>> Samsung HDPTX PHY driver. >>>> >>>> The first part of the series (i.e. PATCH 1 & 2) addresses clock rate >>>> calculation and synchronization issues. Specifically, it fixes edge >>>> cases where the PHY PLL is pre-programmed by an external component (like >>>> a bootloader) or when changing the color depth (bpc) while keeping the >>>> modeline constant. Because the Common Clock Framework .set_rate() >>>> callback might not be invoked if the pixel clock remains unchanged, this >>>> previously led to out-of-sync states between CCF and the actual HDMI PHY >>>> configuration. >>>> >>>> The second part focuses on code cleanups and modernizing the register >>>> access. Now that dw_hdmi_qp driver has fully switched to using >>>> phy_configure(), we can drop the deprecated TMDS rate setup workarounds >>>> and the restrict_rate_change flag logic. Finally, it refactors the >>>> driver to consistently use standard bitfield macros. >>> >>> Sorry looks like I have missed to review this one. >>> Can you please rebase on phy/fixes and send... >> >> I've just verified and it applies cleanly on top of phy/fixes. >> Do you still need a resend? > > Yes please, it didnt apply for me Oh, I used the following branch, hopefully it's the right one: https://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git/log/?h=fixes Regardless, I submitted v2, rebased on the above, while providing a few minor changes: https://lore.kernel.org/all/20260511-hdptx-clk-fixes-v2-0-664e41379cab@collabora.com/ Thanks, Cristian