* Re: Wrong cache size reported on Q6600
2007-06-28 23:31 Wrong cache size reported on Q6600 Con Kolivas
@ 2007-06-28 23:25 ` Kyle McMartin
2007-06-28 23:33 ` Siddha, Suresh B
1 sibling, 0 replies; 5+ messages in thread
From: Kyle McMartin @ 2007-06-28 23:25 UTC (permalink / raw)
To: Con Kolivas; +Cc: linux kernel mailing list
On Fri, Jun 29, 2007 at 09:31:44AM +1000, Con Kolivas wrote:
> This is a Q6600 which has cache size of 8 MB. Unless it's reporting each
> half's effective L2, I think it should be reporting 8192 instead of 4096.
>
Each pair of cores appears to get 4MB of L2, according to the product
brief PDF on Intel's website.
Cheers, Kyle
^ permalink raw reply [flat|nested] 5+ messages in thread
* Wrong cache size reported on Q6600
@ 2007-06-28 23:31 Con Kolivas
2007-06-28 23:25 ` Kyle McMartin
2007-06-28 23:33 ` Siddha, Suresh B
0 siblings, 2 replies; 5+ messages in thread
From: Con Kolivas @ 2007-06-28 23:31 UTC (permalink / raw)
To: linux kernel mailing list
This is a Q6600 which has cache size of 8 MB. Unless it's reporting each
half's effective L2, I think it should be reporting 8192 instead of 4096.
On 2.6.22-rc6:
cat /proc/cpuinfo
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 15
model name : Intel(R) Core(TM)2 Quad CPU @ 2.40GHz
stepping : 7
cpu MHz : 2401.919
cache size : 4096 KB
physical id : 0
siblings : 4
core id : 0
cpu cores : 4
fpu : yes
fpu_exception : yes
cpuid level : 10
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm
constant_tsc pni monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr lahf_lm
bogomips : 4806.38
clflush size : 64
cache_alignment : 64
address sizes : 36 bits physical, 48 bits virtual
power management:
processor : 1
vendor_id : GenuineIntel
cpu family : 6
model : 15
model name : Intel(R) Core(TM)2 Quad CPU @ 2.40GHz
stepping : 7
cpu MHz : 2401.919
cache size : 4096 KB
physical id : 0
siblings : 4
core id : 1
cpu cores : 4
fpu : yes
fpu_exception : yes
cpuid level : 10
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm
constant_tsc pni monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr lahf_lm
bogomips : 4803.73
clflush size : 64
cache_alignment : 64
address sizes : 36 bits physical, 48 bits virtual
power management:
processor : 2
vendor_id : GenuineIntel
cpu family : 6
model : 15
model name : Intel(R) Core(TM)2 Quad CPU @ 2.40GHz
stepping : 7
cpu MHz : 2401.919
cache size : 4096 KB
physical id : 0
siblings : 4
core id : 2
cpu cores : 4
fpu : yes
fpu_exception : yes
cpuid level : 10
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm
constant_tsc pni monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr lahf_lm
bogomips : 4803.86
clflush size : 64
cache_alignment : 64
address sizes : 36 bits physical, 48 bits virtual
power management:
processor : 3
vendor_id : GenuineIntel
cpu family : 6
model : 15
model name : Intel(R) Core(TM)2 Quad CPU @ 2.40GHz
stepping : 7
cpu MHz : 2401.919
cache size : 4096 KB
physical id : 0
siblings : 4
core id : 3
cpu cores : 4
fpu : yes
fpu_exception : yes
cpuid level : 10
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm
constant_tsc pni monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr lahf_lm
bogomips : 4803.93
clflush size : 64
cache_alignment : 64
address sizes : 36 bits physical, 48 bits virtual
power management:
--
-ck
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: Wrong cache size reported on Q6600
2007-06-28 23:31 Wrong cache size reported on Q6600 Con Kolivas
2007-06-28 23:25 ` Kyle McMartin
@ 2007-06-28 23:33 ` Siddha, Suresh B
2007-06-28 23:57 ` Con Kolivas
1 sibling, 1 reply; 5+ messages in thread
From: Siddha, Suresh B @ 2007-06-28 23:33 UTC (permalink / raw)
To: Con Kolivas; +Cc: linux kernel mailing list
On Fri, Jun 29, 2007 at 09:31:44AM +1000, Con Kolivas wrote:
> This is a Q6600 which has cache size of 8 MB. Unless it's reporting each
> half's effective L2, I think it should be reporting 8192 instead of 4096.
There are two L2's, each of 4MB. Each L2 shared by two cores.
thanks,
suresh
>
> On 2.6.22-rc6:
>
> cat /proc/cpuinfo
> processor : 0
> vendor_id : GenuineIntel
> cpu family : 6
> model : 15
> model name : Intel(R) Core(TM)2 Quad CPU @ 2.40GHz
> stepping : 7
> cpu MHz : 2401.919
> cache size : 4096 KB
> physical id : 0
> siblings : 4
> core id : 0
> cpu cores : 4
> fpu : yes
> fpu_exception : yes
> cpuid level : 10
> wp : yes
> flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
> cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm
> constant_tsc pni monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr lahf_lm
> bogomips : 4806.38
> clflush size : 64
> cache_alignment : 64
> address sizes : 36 bits physical, 48 bits virtual
> power management:
>
> processor : 1
> vendor_id : GenuineIntel
> cpu family : 6
> model : 15
> model name : Intel(R) Core(TM)2 Quad CPU @ 2.40GHz
> stepping : 7
> cpu MHz : 2401.919
> cache size : 4096 KB
> physical id : 0
> siblings : 4
> core id : 1
> cpu cores : 4
> fpu : yes
> fpu_exception : yes
> cpuid level : 10
> wp : yes
> flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
> cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm
> constant_tsc pni monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr lahf_lm
> bogomips : 4803.73
> clflush size : 64
> cache_alignment : 64
> address sizes : 36 bits physical, 48 bits virtual
> power management:
>
> processor : 2
> vendor_id : GenuineIntel
> cpu family : 6
> model : 15
> model name : Intel(R) Core(TM)2 Quad CPU @ 2.40GHz
> stepping : 7
> cpu MHz : 2401.919
> cache size : 4096 KB
> physical id : 0
> siblings : 4
> core id : 2
> cpu cores : 4
> fpu : yes
> fpu_exception : yes
> cpuid level : 10
> wp : yes
> flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
> cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm
> constant_tsc pni monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr lahf_lm
> bogomips : 4803.86
> clflush size : 64
> cache_alignment : 64
> address sizes : 36 bits physical, 48 bits virtual
> power management:
>
> processor : 3
> vendor_id : GenuineIntel
> cpu family : 6
> model : 15
> model name : Intel(R) Core(TM)2 Quad CPU @ 2.40GHz
> stepping : 7
> cpu MHz : 2401.919
> cache size : 4096 KB
> physical id : 0
> siblings : 4
> core id : 3
> cpu cores : 4
> fpu : yes
> fpu_exception : yes
> cpuid level : 10
> wp : yes
> flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
> cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm
> constant_tsc pni monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr lahf_lm
> bogomips : 4803.93
> clflush size : 64
> cache_alignment : 64
> address sizes : 36 bits physical, 48 bits virtual
> power management:
>
> --
> -ck
> -
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: Wrong cache size reported on Q6600
2007-06-28 23:33 ` Siddha, Suresh B
@ 2007-06-28 23:57 ` Con Kolivas
2007-06-29 15:31 ` Chuck Ebbert
0 siblings, 1 reply; 5+ messages in thread
From: Con Kolivas @ 2007-06-28 23:57 UTC (permalink / raw)
To: Siddha, Suresh B; +Cc: linux kernel mailing list
On Friday 29 June 2007 09:33, Siddha, Suresh B wrote:
> On Fri, Jun 29, 2007 at 09:31:44AM +1000, Con Kolivas wrote:
> > This is a Q6600 which has cache size of 8 MB. Unless it's reporting each
> > half's effective L2, I think it should be reporting 8192 instead of 4096.
>
> There are two L2's, each of 4MB. Each L2 shared by two cores.
That was what I wasn't sure of as I said above; thanks for clarifying.
--
-ck
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: Wrong cache size reported on Q6600
2007-06-28 23:57 ` Con Kolivas
@ 2007-06-29 15:31 ` Chuck Ebbert
0 siblings, 0 replies; 5+ messages in thread
From: Chuck Ebbert @ 2007-06-29 15:31 UTC (permalink / raw)
To: Con Kolivas; +Cc: Siddha, Suresh B, linux kernel mailing list
On 06/28/2007 07:57 PM, Con Kolivas wrote:
> On Friday 29 June 2007 09:33, Siddha, Suresh B wrote:
>> On Fri, Jun 29, 2007 at 09:31:44AM +1000, Con Kolivas wrote:
>>> This is a Q6600 which has cache size of 8 MB. Unless it's reporting each
>>> half's effective L2, I think it should be reporting 8192 instead of 4096.
>> There are two L2's, each of 4MB. Each L2 shared by two cores.
>
> That was what I wasn't sure of as I said above; thanks for clarifying.
>
You really need to look in /sys/devices/system/cpu/cpuX/cache/ to get
any kind of useful information.
^ permalink raw reply [flat|nested] 5+ messages in thread
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2007-06-28 23:31 Wrong cache size reported on Q6600 Con Kolivas
2007-06-28 23:25 ` Kyle McMartin
2007-06-28 23:33 ` Siddha, Suresh B
2007-06-28 23:57 ` Con Kolivas
2007-06-29 15:31 ` Chuck Ebbert
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