Re: Few interrupts with NO_HZ

Re: Few interrupts with NO_HZ

[Robert Hancock]

Jan Engelhardt wrote:
> Hi,
> 
> 
> this more of an informational question. So:
> 
> kernel version is 2.6.22.1 on i686
> 
> /proc/uptime 
> 9917.81 9140.90 (2h45m)
> 
> /proc/cpuinfo:
>            CPU0
>   0:        282   IO-APIC-edge      timer
> 
> this is kinda neat, I expected much more interrupts than just 282 since 
> boot. What kernel code actually uses the irq0 timer?

The kernel likely switched to using the local APIC timer after bootup..

-- 
Robert Hancock      Saskatoon, SK, Canada
To email, remove "nospam" from hancockr@nospamshaw.ca
Home Page: http://www.roberthancock.com/

Few interrupts with NO_HZ

[Jan Engelhardt]

Hi,


this more of an informational question. So:

kernel version is 2.6.22.1 on i686

/proc/uptime 
9917.81 9140.90 (2h45m)

/proc/cpuinfo:
           CPU0
  0:        282   IO-APIC-edge      timer

this is kinda neat, I expected much more interrupts than just 282 since 
boot. What kernel code actually uses the irq0 timer?


thanks,
	Jan
-- 

Re: Few interrupts with NO_HZ

[Chris Snook]

Jan Engelhardt wrote:
> Hi,
> 
> 
> this more of an informational question. So:
> 
> kernel version is 2.6.22.1 on i686
> 
> /proc/uptime 
> 9917.81 9140.90 (2h45m)
> 
> /proc/cpuinfo:
>            CPU0
>   0:        282   IO-APIC-edge      timer
> 
> this is kinda neat, I expected much more interrupts than just 282 since 
> boot. What kernel code actually uses the irq0 timer?

If you don't have an HPET (and most single-processor systems do not) the kernel 
is probably using the PIT to wake the processor from low-power sleep states, 
since the LAPIC timer is disabled in these states.  If your box is mostly idle, 
you might want to use powertop to figure out why it's entering low power states 
so infrequently.

	-- Chris

Re: Few interrupts with NO_HZ

[Jan Engelhardt]

On Aug 6 2007 09:47, Chris Snook wrote:
>> 
>> this more of an informational question. So:
>> kernel version is 2.6.22.1 on i686
>> /proc/uptime 9917.81 9140.90 (2h45m)
>> /proc/cpuinfo:
>>            CPU0
>>   0:        282   IO-APIC-edge      timer
>> 
>> this is kinda neat, I expected much more interrupts than just 282
>> since boot. What kernel code actually uses the irq0 timer?
>
> If you don't have an HPET (and most single-processor systems do not)

This is an AMD Athlon with 'Thoroughbred' core; it does not seem to
have C-states at all (or: exactly one). It clearly is not idle all the
time, sometimes I run povray. (And 282 has not changed since the
morning.)


	Jan
-- 

Re: Few interrupts with NO_HZ

[Chris Snook]

Jan Engelhardt wrote:
> On Aug 6 2007 09:47, Chris Snook wrote:
>>> this more of an informational question. So:
>>> kernel version is 2.6.22.1 on i686
>>> /proc/uptime 9917.81 9140.90 (2h45m)
>>> /proc/cpuinfo:
>>>            CPU0
>>>   0:        282   IO-APIC-edge      timer
>>>
>>> this is kinda neat, I expected much more interrupts than just 282
>>> since boot. What kernel code actually uses the irq0 timer?
>> If you don't have an HPET (and most single-processor systems do not)
> 
> This is an AMD Athlon with 'Thoroughbred' core; it does not seem to
> have C-states at all (or: exactly one). It clearly is not idle all the
> time, sometimes I run povray. (And 282 has not changed since the
> morning.)
> 
> 
> 	Jan

In that case, it's probably the early bootstrap code that runs before the TSC is 
calibrated.  PIT sucks, but it sucks very reliably, so it's a good basis for 
calibrating the other timekeeping devices.  Once you have something better set 
up, you don't need it anymore if you're not doing C-state transitions.

	-- Chris

Re: Few interrupts with NO_HZ

[Kyle McMartin]

On Mon, Aug 06, 2007 at 12:52:36PM +0200, Jan Engelhardt wrote:
>            CPU0
>   0:        282   IO-APIC-edge      timer

Look at the LOC line.